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[/] [a-z80/] [trunk/] [cpu/] [control/] [decode_state.v] - Diff between revs 3 and 13

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Rev 3 Rev 13
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Fri Oct 31 20:27:41 2014"
 
// CREATED              "Wed Dec 07 00:18:12 2016"
 
 
 
 
 
module decode_state(
 
module decode_state(
 
        ctl_state_iy_set,
 
        ctl_state_iy_set,
 
        ctl_state_ixiy_clr,
 
        ctl_state_ixiy_clr,
 
        ctl_state_ixiy_we,
 
        ctl_state_ixiy_we,
 
        ctl_state_halt_set,
 
        ctl_state_halt_set,
 
        ctl_state_tbl_clr,
 
 
 
        ctl_state_tbl_ed_set,
 
        ctl_state_tbl_ed_set,
 
        ctl_state_tbl_cb_set,
 
        ctl_state_tbl_cb_set,
 
        ctl_state_alu,
 
        ctl_state_alu,
 
        clk,
 
        clk,
 
        address_is_1,
 
        address_is_1,
 
        ctl_repeat_we,
 
        ctl_repeat_we,
 
        in_intr,
 
        in_intr,
 
        in_nmi,
 
        in_nmi,
 
        nreset,
 
        nreset,
 
 
 
        ctl_state_tbl_we,
 
 
 
        hold_clk_wait,
 
        in_halt,
 
        in_halt,
 
        table_cb,
 
        table_cb,
 
        table_ed,
 
        table_ed,
 
        table_xx,
 
        table_xx,
 
        use_ix,
 
        use_ix,
Line 44... Line 45... 
 
 
 
 
input wire      ctl_state_iy_set;
 
input wire      ctl_state_iy_set;
 
input wire      ctl_state_ixiy_clr;
 
input wire      ctl_state_ixiy_clr;
 
input wire      ctl_state_ixiy_we;
 
input wire      ctl_state_ixiy_we;
 
input wire      ctl_state_halt_set;
 
input wire      ctl_state_halt_set;
 
input wire      ctl_state_tbl_clr;
 
 
 
input wire      ctl_state_tbl_ed_set;
 
input wire      ctl_state_tbl_ed_set;
 
input wire      ctl_state_tbl_cb_set;
 
input wire      ctl_state_tbl_cb_set;
 
input wire      ctl_state_alu;
 
input wire      ctl_state_alu;
 
input wire      clk;
 
input wire      clk;
 
input wire      address_is_1;
 
input wire      address_is_1;
 
input wire      ctl_repeat_we;
 
input wire      ctl_repeat_we;
 
input wire      in_intr;
 
input wire      in_intr;
 
input wire      in_nmi;
 
input wire      in_nmi;
 
input wire      nreset;
 
input wire      nreset;
 
 
 
input wire      ctl_state_tbl_we;
 
 
 
input wire      hold_clk_wait;
 
output reg      in_halt;
 
output reg      in_halt;
 
output wire     table_cb;
 
output wire     table_cb;
 
output wire     table_ed;
 
output wire     table_ed;
 
output wire     table_xx;
 
output wire     table_xx;
 
output wire     use_ix;
 
output wire     use_ix;
Line 69... Line 71... 
reg     DFFE_instIY1;
 
reg     DFFE_instIY1;
 
reg     DFFE_inst4;
 
reg     DFFE_inst4;
 
reg     DFFE_instED;
 
reg     DFFE_instED;
 
reg     DFFE_instCB;
 
reg     DFFE_instCB;
 
wire    SYNTHESIZED_WIRE_0;
 
wire    SYNTHESIZED_WIRE_0;
 
 
 
wire    SYNTHESIZED_WIRE_1;
 
 
 
wire    SYNTHESIZED_WIRE_5;
 
wire    SYNTHESIZED_WIRE_4;
 
wire    SYNTHESIZED_WIRE_4;
 
wire    SYNTHESIZED_WIRE_3;
 
 
 
 
 
 
 
assign  in_alu = ctl_state_alu;
 
assign  in_alu = ctl_state_alu;
 
assign  table_cb = DFFE_instCB;
 
assign  table_cb = DFFE_instCB;
 
assign  table_ed = DFFE_instED;
 
assign  table_ed = DFFE_instED;
 
assign  use_ix = DFFE_inst4;
 
assign  use_ix = DFFE_inst4;
 
 
 
 
 
 
 
 
 
 
 
 
 
assign  repeat_en =  ~DFFE_instNonRep;
 
assign  repeat_en =  ~DFFE_instNonRep;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_4 = ctl_state_tbl_clr | ctl_state_tbl_ed_set | ctl_state_tbl_cb_set;
 
 
 
 
 
 
 
assign  use_ixiy = DFFE_instIY1 | DFFE_inst4;
 
assign  use_ixiy = DFFE_instIY1 | DFFE_inst4;
 
 
 
 
 
assign  table_xx = ~(DFFE_instED | DFFE_instCB);
 
assign  table_xx = ~(DFFE_instED | DFFE_instCB);
 
 
 
 
 
 
 
 
Line 103... Line 104... 
        end
 
        end
 
end
 
end
 
 
 
 
 
assign  SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
 
assign  SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
 
 
 
 
 
assign  SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
 
assign  SYNTHESIZED_WIRE_5 = ctl_state_tbl_we & SYNTHESIZED_WIRE_1;
 
 
 
 
 
 
 
assign  SYNTHESIZED_WIRE_4 = in_nmi | in_intr;
 
 
 
 
 
 
 
assign  SYNTHESIZED_WIRE_1 =  ~hold_clk_wait;
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_instCB <= 0;
 
        DFFE_instCB <= 0;
 
        end
 
        end
 
else
 
else
 
if (SYNTHESIZED_WIRE_4)
 
if (SYNTHESIZED_WIRE_5)
 
        begin
 
        begin
 
        DFFE_instCB <= ctl_state_tbl_cb_set;
 
        DFFE_instCB <= ctl_state_tbl_cb_set;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 127... Line 132... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_instED <= 0;
 
        DFFE_instED <= 0;
 
        end
 
        end
 
else
 
else
 
if (SYNTHESIZED_WIRE_4)
 
if (SYNTHESIZED_WIRE_5)
 
        begin
 
        begin
 
        DFFE_instED <= ctl_state_tbl_ed_set;
 
        DFFE_instED <= ctl_state_tbl_ed_set;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 142... Line 147... 
        begin
 
        begin
 
        in_halt <= 0;
 
        in_halt <= 0;
 
        end
 
        end
 
else
 
else
 
        begin
 
        begin
 
        in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
 
        in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_4;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)

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