| Line 3644... |
Line 3644... |
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1;
|
ctl_flags_cf_we=1;
|
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
|
ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
| Line 3683... |
Line 3683... |
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
end
|
end
|
|
|
if (pla[44]) begin
|
if (pla[44]) begin
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
|
ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
end
|
end
|
|
|
if (pla[51]) begin
|
if (pla[51]) begin
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end
|
ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; /* ED-table prefix */ end
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
|
end
|
end
|
|
|
if (pla[76]) begin
|
if (pla[76]) begin
|
| Line 3840... |
Line 3840... |
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_alu_sel_op2_neg=flags_sf;
|
ctl_alu_sel_op2_neg=flags_sf;
|
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */ end
|
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */ end
|
end
|
end
|
|
|
// Default instruction fetch (M1) state machine
|
// Default instruction fetch (M1) state machine
|
if (1) begin
|
if (1) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
| Line 3853... |
Line 3853... |
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end
|
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
|
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */
|
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */
|
ctl_state_tbl_clr=~setCBED; /* Clear CB/ED prefix */
|
ctl_state_tbl_we=1; /* Clear CB/ED prefix if not explicitly set */
|
ctl_ir_we=1;
|
ctl_ir_we=1;
|
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
|
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */
|
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
