| Line 2987... |
Line 2987... |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M3 && T2) begin fMWrite=1;
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if (M3 && T2) begin fMWrite=1;
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ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
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ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
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ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
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ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf;
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if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end
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ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
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ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
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ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
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if (M4 && T1) begin
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if (M4 && T1) begin
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M4 && T2) begin
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if (M4 && T2) begin
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M4 && T3) begin
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if (M4 && T3) begin
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M4 && T4) begin
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if (M4 && T4) begin
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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| Line 3116... |
Line 3110... |
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
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ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
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end else begin
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end else begin
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ctl_alu_core_hf=1;
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ctl_alu_core_hf=1;
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end
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end
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ctl_flags_cf_we=1; end
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ctl_flags_cf_we=1; end
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if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf;
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if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end
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ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
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ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
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ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
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ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
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if (M4 && T1) begin
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if (M4 && T1) begin
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M4 && T2) begin
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if (M4 && T2) begin
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M4 && T3) begin
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if (M4 && T3) begin
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M4 && T4) begin
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if (M4 && T4) begin
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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