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// Module: control/decode_state.v
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// Module: control/decode_state.v
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output reg ctl_state_iy_set,
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output reg ctl_state_iy_set,
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output reg ctl_state_ixiy_clr,
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output reg ctl_state_ixiy_clr,
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output reg ctl_state_ixiy_we,
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output reg ctl_state_ixiy_we,
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output reg ctl_state_halt_set,
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output reg ctl_state_halt_set,
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output reg ctl_state_tbl_clr,
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output reg ctl_state_tbl_ed_set,
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output reg ctl_state_tbl_ed_set,
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output reg ctl_state_tbl_cb_set,
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output reg ctl_state_tbl_cb_set,
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output reg ctl_state_alu,
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output reg ctl_state_alu,
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output reg ctl_repeat_we,
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output reg ctl_repeat_we,
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output reg ctl_state_tbl_we,
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// Module: control/interrupts.v
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// Module: control/interrupts.v
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output reg ctl_iff1_iff2,
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output reg ctl_iff1_iff2,
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output reg ctl_iffx_we,
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output reg ctl_iffx_we,
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output reg ctl_iffx_bit,
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output reg ctl_iffx_bit,
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