| Line 76... |
Line 76... |
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// Detects unknown instructions by signalling the known ones
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// Detects unknown instructions by signalling the known ones
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reg validPLA; // Valid PLA asserts this reg
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reg validPLA; // Valid PLA asserts this reg
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// Activates a state machine to compute WZ=IX+d; takes 5T cycles
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// Activates a state machine to compute WZ=IX+d; takes 5T cycles
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reg ixy_d; // Compute WX=IX+d
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reg ixy_d; // Compute WX=IX+d
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// Signals the setting of IX/IY and CB/ED prefix flags; inhibits clearing them
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// Signals the setting of IX/IY prefix flags; inhibits clearing them
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reg setIXIY; // Set IX/IY flag at the next T cycle
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reg setIXIY; // Set IX/IY flag at the next T cycle
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reg setCBED; // Set CB or ED flag at the next T cycle
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// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
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// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
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reg nonRep; // Non-repeating block instruction
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reg nonRep; // Non-repeating block instruction
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// Suspends incrementing PC through address latch unless in HALT or interrupt mode
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// Suspends incrementing PC through address latch unless in HALT or interrupt mode
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reg pc_inc_hold; // Normally 0 unless in one of those modes
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reg pc_inc_hold; // Normally 0 unless in one of those modes
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| Line 137... |
Line 136... |
// Reset global machine cycle functions
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// Reset global machine cycle functions
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fFetch = M1; // Fetch is aliased to M1
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fFetch = M1; // Fetch is aliased to M1
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fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
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fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
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ixy_d = 0;
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ixy_d = 0;
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setIXIY = 0;
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setIXIY = 0;
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setCBED = 0;
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nonRep = 0;
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nonRep = 0;
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pc_inc_hold = 0;
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pc_inc_hold = 0;
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// State-based signal assignment; code generated from Timings spreadsheet
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// State-based signal assignment; code generated from Timings spreadsheet
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