| Line 1... |
Line 1... |
#!/usr/bin/env python
|
#!/usr/bin/env python3
|
#
|
#
|
# This script reads and parses selected Verilog and SystemVerilog modules
|
# This script reads and parses selected Verilog and SystemVerilog modules
|
# and generates a set of Verilog include files for the control block.
|
# and generates a set of Verilog include files for the control block.
|
#
|
#
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
| Line 20... |
Line 20... |
import os
|
import os
|
|
|
with open('../top-level-files.txt') as f:
|
with open('../top-level-files.txt') as f:
|
files = f.read().splitlines()
|
files = f.read().splitlines()
|
|
|
# Create 2 files that should be included in the execution engine block:
|
# Create 2 files that should be included by the execution engine:
|
# 1. A module arguments section
|
# 1. A file listing all control signals
|
# 2. A file containing the code to initialize control wires to zero
|
# 2. A file containing statements initializing control signals to zero
|
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
|
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
|
file1.write("// Automatically generated by genref.py\n")
|
file1.write("// Automatically generated by genref.py\n")
|
file0.write("// Automatically generated by genref.py\n")
|
file0.write("// Automatically generated by genref.py\n")
|
|
|
# Read and parse each file from the list of input files
|
# Read and parse each file from the list of input files
|
| Line 37... |
Line 37... |
with open('../' + infile, "r") as f:
|
with open('../' + infile, "r") as f:
|
for line in f:
|
for line in f:
|
info = line.split()
|
info = line.split()
|
# input wire register case
|
# input wire register case
|
if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"):
|
if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"):
|
wires.append(info[2].translate(None, ';,'))
|
wires.append(info[2].strip(';,'))
|
# input wire [1:0] bus case
|
# input wire bus case (ex. "[1:0]")
|
if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
|
if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
|
wires.append(info[2] + " " + info[3].translate(None, ';,'))
|
wires.append(info[2] + " " + info[3].strip(';,'))
|
|
|
if len(wires)>0:
|
if len(wires)>0:
|
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
|
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
|
print "MODULE: " + infile
|
print ("MODULE:", infile)
|
file0.write("\n// Module: " + infile + "\n")
|
file0.write("\n// Module: " + infile + "\n")
|
file1.write("\n// Module: " + infile + "\n")
|
file1.write("\n// Module: " + infile + "\n")
|
for wire in wires:
|
for wire in wires:
|
print " " + wire
|
print (" ", wire)
|
file1.write("output logic " + wire + ",\n")
|
file1.write("output reg " + wire + ",\n")
|
# To the exec include, write bus with the length field (if the wire is a bus)
|
|
# To the zero include, skip bus width field
|
|
if "[" in wire:
|
if "[" in wire:
|
file0.write(wire.split()[1] + " = 0;\n")
|
file0.write(wire.split()[1] + " = 0;\n")
|
else:
|
else:
|
file0.write(wire + " = 0;\n")
|
file0.write(wire + " = 0;\n")
|
|
|
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
|
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
|
os.utime("execute.sv", None)
|
os.utime("execute.v", None)
|
|
|
No newline at end of file
|
No newline at end of file
|
