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// Altera or its authorized distributors.  Please refer to the 

// Altera or its authorized distributors.  Please refer to the 

// applicable agreement for further details.

// applicable agreement for further details.

// PROGRAM              "Quartus II 64-Bit"

// PROGRAM              "Quartus II 64-Bit"

// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"

// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"

module interrupts(

module interrupts(

        ctl_iff1_iff2,

        ctl_iff1_iff2,

        nmi,

        nmi,

        setM1,

        setM1,

        ctl_im_we,

        ctl_im_we,

        clk,

        clk,

        ctl_no_ints,

        ctl_no_ints,

        nreset,

        nreset,

        db,

        db,

        iff2,

        iff2,

        im1,

        im1,

        im2,

        im2,

        in_nmi,

        in_nmi,

        in_intr

        in_intr

input wire      ctl_im_we;

input wire      ctl_im_we;

input wire      clk;

input wire      clk;

input wire      ctl_no_ints;

input wire      ctl_no_ints;

input wire      nreset;

input wire      nreset;

input wire      [1:0] db;

input wire      [1:0] db;

output wire     iff2;

output wire     iff2;

output reg      im1;

output reg      im1;

output reg      im2;

output reg      im2;

output wire     in_nmi;

output wire     in_nmi;

output wire     in_intr;

output wire     in_intr;

wire    in_intr_ALTERA_SYNTHESIZED;

wire    in_intr_ALTERA_SYNTHESIZED;

reg     in_nmi_ALTERA_SYNTHESIZED;

reg     in_nmi_ALTERA_SYNTHESIZED;

reg     int_armed;

reg     int_armed;

reg     nmi_armed;

reg     nmi_armed;

wire    test1;

wire    test1;

assign  in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;

assign  in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;

assign  SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;

assign  SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;

assign  test1 = setM1 & SYNTHESIZED_WIRE_8;

assign  test1 = setM1 & SYNTHESIZED_WIRE_8;

always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)

always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)

always@(posedge clk or negedge SYNTHESIZED_WIRE_15)

always@(posedge clk or negedge SYNTHESIZED_WIRE_15)

begin

begin

if (!SYNTHESIZED_WIRE_15)

if (!SYNTHESIZED_WIRE_15)

        begin

        begin

        end

        end

else

else

if (SYNTHESIZED_WIRE_17)

if (SYNTHESIZED_WIRE_17)

        begin

        begin

        end

        end

end

end

always@(posedge clk or negedge SYNTHESIZED_WIRE_21)

always@(posedge clk or negedge SYNTHESIZED_WIRE_21)

assign  SYNTHESIZED_WIRE_7 =  ~in_nmi_ALTERA_SYNTHESIZED;

assign  SYNTHESIZED_WIRE_7 =  ~in_nmi_ALTERA_SYNTHESIZED;

assign  SYNTHESIZED_WIRE_14 =  ~in_nmi_ALTERA_SYNTHESIZED;

assign  SYNTHESIZED_WIRE_14 =  ~in_nmi_ALTERA_SYNTHESIZED;

assign  in_nmi = in_nmi_ALTERA_SYNTHESIZED;

assign  in_nmi = in_nmi_ALTERA_SYNTHESIZED;

assign  in_intr = in_intr_ALTERA_SYNTHESIZED;

assign  in_intr = in_intr_ALTERA_SYNTHESIZED;

endmodule

endmodule

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