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[/] [a-z80/] [trunk/] [cpu/] [control/] [ir.v] - Diff between revs 13 and 16
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Rev 16 |
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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Fri Feb 26 22:23:08 2016"
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// CREATED "Sat Dec 10 08:56:46 2016"
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module ir(
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module ir(
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ctl_ir_we,
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ctl_ir_we,
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clk,
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clk,
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nreset,
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nreset,
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hold_clk_wait,
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nhold_clk_wait,
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db,
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db,
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opcode
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opcode
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);
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);
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input wire ctl_ir_we;
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input wire ctl_ir_we;
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input wire clk;
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input wire clk;
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input wire nreset;
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input wire nreset;
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input wire hold_clk_wait;
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input wire nhold_clk_wait;
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input wire [7:0] db;
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input wire [7:0] db;
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output reg [7:0] opcode;
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output reg [7:0] opcode;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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assign SYNTHESIZED_WIRE_0 = ~hold_clk_wait;
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assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;
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assign SYNTHESIZED_WIRE_1 = ctl_ir_we & SYNTHESIZED_WIRE_0;
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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opcode[7:0] <= 8'b00000000;
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opcode[7:0] <= 8'b00000000;
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end
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end
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else
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else
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if (SYNTHESIZED_WIRE_1)
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if (SYNTHESIZED_WIRE_0)
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begin
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begin
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opcode[7:0] <= db[7:0];
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opcode[7:0] <= db[7:0];
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end
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end
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end
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end
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