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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sat Feb 27 08:32:59 2016"
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// CREATED "Thu Dec 08 21:08:44 2016"
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module resets(
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module resets(
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reset_in,
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reset_in,
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clk,
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clk,
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M1,
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M1,
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T2,
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T2,
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fpga_reset,
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fpga_reset,
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hold_clk_wait,
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clrpc,
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clrpc,
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nreset
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nreset
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);
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);
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input wire reset_in;
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input wire reset_in;
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input wire clk;
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input wire clk;
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input wire M1;
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input wire M1;
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input wire T2;
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input wire T2;
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input wire fpga_reset;
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input wire fpga_reset;
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input wire hold_clk_wait;
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output wire clrpc;
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output wire clrpc;
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output wire nreset;
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output wire nreset;
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reg clrpc_int;
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reg clrpc_int;
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wire nclk;
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wire nclk;
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reg x1;
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reg x1;
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wire x2;
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wire x2;
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wire x3;
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wire x3;
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wire SYNTHESIZED_WIRE_8;
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wire SYNTHESIZED_WIRE_1;
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reg SYNTHESIZED_WIRE_9;
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reg DFF_res3;
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reg SYNTHESIZED_WIRE_10;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_1;
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reg SYNTHESIZED_WIRE_12;
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reg SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_6;
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reg DFFE_intr_ff3;
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reg SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_3;
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reg SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_16;
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wire SYNTHESIZED_WIRE_9;
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assign nreset = SYNTHESIZED_WIRE_6;
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assign nreset = SYNTHESIZED_WIRE_9;
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always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
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always@(posedge nclk or negedge SYNTHESIZED_WIRE_11)
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begin
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begin
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if (!SYNTHESIZED_WIRE_8)
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if (!SYNTHESIZED_WIRE_11)
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begin
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begin
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x1 <= 1;
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x1 <= 1;
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end
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end
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else
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else
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begin
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begin
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x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
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x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
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end
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end
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end
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end
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assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFF_res3 | SYNTHESIZED_WIRE_10;
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assign clrpc = clrpc_int | SYNTHESIZED_WIRE_12 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_13;
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assign SYNTHESIZED_WIRE_1 = ~reset_in;
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assign SYNTHESIZED_WIRE_1 = ~reset_in;
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assign x2 = x1 & SYNTHESIZED_WIRE_11;
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assign x2 = x1 & SYNTHESIZED_WIRE_14;
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assign SYNTHESIZED_WIRE_11 = M1 & T2;
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assign SYNTHESIZED_WIRE_14 = M1 & T2;
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assign x3 = x1 & SYNTHESIZED_WIRE_3;
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assign x3 = x1 & SYNTHESIZED_WIRE_3;
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assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
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assign SYNTHESIZED_WIRE_9 = ~SYNTHESIZED_WIRE_15;
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assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
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assign SYNTHESIZED_WIRE_16 = ~hold_clk_wait;
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assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_14;
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assign nclk = ~clk;
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assign nclk = ~clk;
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assign SYNTHESIZED_WIRE_8 = ~fpga_reset;
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assign SYNTHESIZED_WIRE_11 = ~fpga_reset;
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always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
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always@(posedge nclk)
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begin
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begin
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if (!SYNTHESIZED_WIRE_8)
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if (SYNTHESIZED_WIRE_16)
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begin
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begin
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SYNTHESIZED_WIRE_12 <= 1;
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DFFE_intr_ff3 <= SYNTHESIZED_WIRE_12;
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end
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else
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begin
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SYNTHESIZED_WIRE_12 <= x3;
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end
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end
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end
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end
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always@(posedge nclk)
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always@(posedge nclk)
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begin
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begin
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if (SYNTHESIZED_WIRE_16)
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begin
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begin
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SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
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SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_15;
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end
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end
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end
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end
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always@(posedge nclk)
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always@(posedge nclk)
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begin
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begin
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if (SYNTHESIZED_WIRE_16)
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begin
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begin
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SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
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SYNTHESIZED_WIRE_12 <= SYNTHESIZED_WIRE_13;
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end
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end
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end
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end
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always@(posedge nclk)
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always@(posedge clk or negedge SYNTHESIZED_WIRE_11)
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begin
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begin
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if (!SYNTHESIZED_WIRE_11)
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begin
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SYNTHESIZED_WIRE_15 <= 1;
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end
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else
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begin
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begin
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DFF_res3 <= SYNTHESIZED_WIRE_9;
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SYNTHESIZED_WIRE_15 <= x3;
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end
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end
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end
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end
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always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
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always@(posedge nclk or negedge SYNTHESIZED_WIRE_9)
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begin
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begin
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if (!SYNTHESIZED_WIRE_6)
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if (!SYNTHESIZED_WIRE_9)
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begin
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begin
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clrpc_int <= 0;
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clrpc_int <= 0;
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end
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end
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else
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else
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begin
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begin
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clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
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clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_14;
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end
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end
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end
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end
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endmodule
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endmodule
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