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[/] [a-z80/] [trunk/] [cpu/] [control/] [resets.v] - Diff between revs 13 and 16

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// Copyright (C) 1991-2013 Altera Corporation
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
// applicable agreement for further details.
 
 
// PROGRAM              "Quartus II 64-Bit"
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Thu Dec 08 21:08:44 2016"
// CREATED              "Sat Dec 10 08:57:54 2016"
 
 
module resets(
module resets(
        reset_in,
        reset_in,
        clk,
        clk,
        M1,
        M1,
        T2,
        T2,
        fpga_reset,
        fpga_reset,
        hold_clk_wait,
        nhold_clk_wait,
        clrpc,
        clrpc,
        nreset
        nreset
);
);
 
 
 
 
input wire      reset_in;
input wire      reset_in;
input wire      clk;
input wire      clk;
input wire      M1;
input wire      M1;
input wire      T2;
input wire      T2;
input wire      fpga_reset;
input wire      fpga_reset;
input wire      hold_clk_wait;
input wire      nhold_clk_wait;
output wire     clrpc;
output wire     clrpc;
output wire     nreset;
output wire     nreset;
 
 
reg     clrpc_int;
reg     clrpc_int;
wire    nclk;
wire    nclk;
reg     x1;
reg     x1;
wire    x2;
wire    x2;
wire    x3;
wire    x3;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_8;
wire    SYNTHESIZED_WIRE_1;
wire    SYNTHESIZED_WIRE_1;
reg     SYNTHESIZED_WIRE_12;
reg     SYNTHESIZED_WIRE_9;
reg     DFFE_intr_ff3;
reg     DFFE_intr_ff3;
reg     SYNTHESIZED_WIRE_13;
reg     SYNTHESIZED_WIRE_10;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_3;
wire    SYNTHESIZED_WIRE_3;
reg     SYNTHESIZED_WIRE_15;
reg     SYNTHESIZED_WIRE_12;
wire    SYNTHESIZED_WIRE_16;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_9;
 
 
 
assign  nreset = SYNTHESIZED_WIRE_9;
assign  nreset = SYNTHESIZED_WIRE_6;
 
 
 
 
 
 
 
 
always@(posedge nclk or negedge SYNTHESIZED_WIRE_11)
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
begin
begin
if (!SYNTHESIZED_WIRE_11)
if (!SYNTHESIZED_WIRE_8)
        begin
        begin
        x1 <= 1;
        x1 <= 1;
        end
        end
else
else
        begin
        begin
        x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
        x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
        end
        end
end
end
 
 
assign  clrpc = clrpc_int | SYNTHESIZED_WIRE_12 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_13;
assign  clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10;
 
 
assign  SYNTHESIZED_WIRE_1 =  ~reset_in;
assign  SYNTHESIZED_WIRE_1 =  ~reset_in;
 
 
assign  x2 = x1 & SYNTHESIZED_WIRE_14;
assign  x2 = x1 & SYNTHESIZED_WIRE_11;
 
 
assign  SYNTHESIZED_WIRE_14 = M1 & T2;
assign  SYNTHESIZED_WIRE_11 = M1 & T2;
 
 
assign  x3 = x1 & SYNTHESIZED_WIRE_3;
assign  x3 = x1 & SYNTHESIZED_WIRE_3;
 
 
assign  SYNTHESIZED_WIRE_9 =  ~SYNTHESIZED_WIRE_15;
assign  SYNTHESIZED_WIRE_6 =  ~SYNTHESIZED_WIRE_12;
 
 
assign  SYNTHESIZED_WIRE_16 =  ~hold_clk_wait;
 
 
 
assign  SYNTHESIZED_WIRE_3 =  ~SYNTHESIZED_WIRE_14;
assign  SYNTHESIZED_WIRE_3 =  ~SYNTHESIZED_WIRE_11;
 
 
assign  nclk =  ~clk;
assign  nclk =  ~clk;
 
 
assign  SYNTHESIZED_WIRE_11 =  ~fpga_reset;
assign  SYNTHESIZED_WIRE_8 =  ~fpga_reset;
 
 
 
 
always@(posedge nclk)
always@(posedge nclk)
begin
begin
if (SYNTHESIZED_WIRE_16)
if (nhold_clk_wait)
        begin
        begin
        DFFE_intr_ff3 <= SYNTHESIZED_WIRE_12;
        DFFE_intr_ff3 <= SYNTHESIZED_WIRE_9;
        end
        end
end
end
 
 
 
 
always@(posedge nclk)
always@(posedge nclk)
begin
begin
if (SYNTHESIZED_WIRE_16)
if (nhold_clk_wait)
        begin
        begin
        SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_15;
        SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
        end
        end
end
end
 
 
 
 
always@(posedge nclk)
always@(posedge nclk)
begin
begin
if (SYNTHESIZED_WIRE_16)
if (nhold_clk_wait)
        begin
        begin
        SYNTHESIZED_WIRE_12 <= SYNTHESIZED_WIRE_13;
        SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
        end
        end
end
end
 
 
 
 
always@(posedge clk or negedge SYNTHESIZED_WIRE_11)
always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
begin
begin
if (!SYNTHESIZED_WIRE_11)
if (!SYNTHESIZED_WIRE_8)
        begin
        begin
        SYNTHESIZED_WIRE_15 <= 1;
        SYNTHESIZED_WIRE_12 <= 1;
        end
        end
else
else
        begin
        begin
        SYNTHESIZED_WIRE_15 <= x3;
        SYNTHESIZED_WIRE_12 <= x3;
        end
        end
end
end
 
 
 
 
always@(posedge nclk or negedge SYNTHESIZED_WIRE_9)
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
begin
begin
if (!SYNTHESIZED_WIRE_9)
if (!SYNTHESIZED_WIRE_6)
        begin
        begin
        clrpc_int <= 0;
        clrpc_int <= 0;
        end
        end
else
else
        begin
        begin
        clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_14;
        clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
        end
        end
end
end
 
 
 
 
endmodule
endmodule
 
 

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