URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [control/] [test_decode.sv] - Diff between revs 3 and 8
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 8 |
| Line 130... |
Line 130... |
.M1(M1_sig) , // input M1_sig
|
.M1(M1_sig) , // input M1_sig
|
.M2(M2_sig) , // input M2_sig
|
.M2(M2_sig) , // input M2_sig
|
.M3(M3_sig) , // input M3_sig
|
.M3(M3_sig) , // input M3_sig
|
.M4(M4_sig) , // input M4_sig
|
.M4(M4_sig) , // input M4_sig
|
.M5(M5_sig) , // input M5_sig
|
.M5(M5_sig) , // input M5_sig
|
.M6(M6_sig) , // input M6_sig
|
|
.T1(T1_sig) , // input T1_sig
|
.T1(T1_sig) , // input T1_sig
|
.T2(T2_sig) , // input T2_sig
|
.T2(T2_sig) , // input T2_sig
|
.T3(T3_sig) , // input T3_sig
|
.T3(T3_sig) , // input T3_sig
|
.T4(T4_sig) , // input T4_sig
|
.T4(T4_sig) , // input T4_sig
|
.T5(T5_sig) , // input T5_sig
|
.T5(T5_sig) , // input T5_sig
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
