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[/] [a-z80/] [trunk/] [cpu/] [control/] [test_reset.sv] - Diff between revs 8 and 13

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Rev 8 Rev 13
Line 21... Line 21...
logic reset_in = 0;
logic reset_in = 0;
logic M1 = 0;
logic M1 = 0;
logic T2 = 0;
logic T2 = 0;
 
 
wire clrpc;            // Load 0 to PC
wire clrpc;            // Load 0 to PC
 
wire hold_clk_wait;    // Hold clrpc
wire nreset;           // Internal inverted reset signal
wire nreset;           // Internal inverted reset signal
 
 
 
assign hold_clk_wait = 0; // Will not test this case
 
 
// ----------------- TEST -------------------
// ----------------- TEST -------------------
initial begin
initial begin
    // Test normal reset sequence - 3 clocks long
    // Test normal reset sequence - 3 clocks long
    `T reset_in = 1;
    `T reset_in = 1;
    `T `T `T reset_in = 0;
    `T `T `T reset_in = 0;

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