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[/] [a-z80/] [trunk/] [cpu/] [control/] [test_reset.sv] - Diff between revs 3 and 8
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Rev 8 |
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Line 6... |
module test_reset;
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module test_reset;
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// ----------------- CLOCKS AND RESET -----------------
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// ----------------- CLOCKS AND RESET -----------------
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`define T #2
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`define T #2
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bit clk = 1;
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bit clk = 1;
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initial repeat (30) #1 clk = ~clk;
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initial repeat (40) #1 clk = ~clk;
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// Specific to FPGA, some modules in the schematic need to be pre-initialized
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// Specific to FPGA, some modules in the schematic need to be pre-initialized
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reg fpga_reset = 1;
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reg fpga_reset = 1;
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always_latch
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always_latch
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if (clk) fpga_reset <= 0;
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if (clk) fpga_reset <= 0;
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| Line 28... |
Line 28... |
// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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initial begin
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initial begin
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// Test normal reset sequence - 3 clocks long
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// Test normal reset sequence - 3 clocks long
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`T reset_in = 1;
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`T reset_in = 1;
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`T `T `T reset_in = 0;
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`T `T `T reset_in = 0;
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`T assert(nreset==0 && clrpc==0);
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`T assert(nreset==0);
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// Out of the reset for several more cycles
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// Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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// Test special reset sequence: a reset pin is briefly
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// Test special reset sequence: a reset pin is briefly
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// asserted at M1/T1 and CLRPC should hold until the next
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// asserted at M1/T1 and CLRPC should hold until the next
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// M1/T2
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// M1/T2
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`T reset_in = 1; M1=1;
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`T reset_in = 1; M1=1;
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`T reset_in = 0; M1=1; T2=1;
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`T reset_in = 0; M1=1; T2=1;
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