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https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [export.py] - Diff between revs 8 and 13
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| Rev 8 |
Rev 13 |
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Line 21... |
from shutil import copyfile
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from shutil import copyfile
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if len(sys.argv) != 2:
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if len(sys.argv) != 2:
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print ("\nUsage: export.py <destination-folder>\n")
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print ("\nUsage: export.py <destination-folder>\n")
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print ("Copies all core A-Z80 Verilog files to a destination of your choice.")
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print ("Copies all core A-Z80 Verilog files to a destination of your choice.")
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print ("The files copied are necessary and sufficient to include with your project.")
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print ("The files copied are necessary and sufficient to include with your project.\n")
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print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
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print ("copy and use data_pins_lattice.v file instead.")
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exit(-1)
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exit(-1)
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dest = sys.argv[1]
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dest = sys.argv[1]
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total = 0
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total = 0
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