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#!/usr/bin/env python3
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#!/usr/bin/env python3
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#
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#
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# This script exports all core A-Z80 Verilog files to a destination of your choice.
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# This script exports all core A-Z80 Verilog files to a destination folder of your choice.
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# The files copied are necessary and sufficient to include with your custom project.
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# Add all Verilog files (*.v) to your project and ensure that Verilog include files (*.vh)
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# are on the include path.
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014, 2016 Goran Devic, www.baltazarstudios.com
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# Copyright (C) 2014,2017 Goran Devic, www.baltazarstudios.com
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#
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#
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# This program is free software; you can redistribute it and/or modify it
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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# any later version.
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import os
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import os
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from shutil import copyfile
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from shutil import copyfile
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if len(sys.argv) != 2:
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if len(sys.argv) != 2:
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print ("\nUsage: export.py <destination-folder>\n")
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print ("\nUsage: export.py <destination-folder>\n")
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print ("Copies all core A-Z80 Verilog files to a destination of your choice.")
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print ("Copies all core A-Z80 Verilog files to a destination folder of your choice.")
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print ("The files copied are necessary and sufficient to include with your project.\n")
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print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
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print ("copy and use data_pins_lattice.v file instead.")
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exit(-1)
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exit(-1)
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dest = sys.argv[1]
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dest = sys.argv[1]
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total = 0
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total = 0
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files = int(infile[6:])
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files = int(infile[6:])
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if total != files:
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if total != files:
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print ("ERROR: Incorrect number of files copied!")
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print ("ERROR: Incorrect number of files copied!")
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exit(-1)
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exit(-1)
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else:
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else:
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print ("\nDone copying {0} files.".format(files))
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print ("\nDone copying {0} files.\n".format(files))
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if not os.path.isfile(infile):
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if not os.path.isfile(infile):
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continue
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continue
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name = os.path.basename(infile)
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name = os.path.basename(infile)
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print ('Copying', infile)
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print ('Copying', infile)
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with open(dest + '/' + name, 'wt') as f:
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with open(dest + '/' + name, 'wt') as f:
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f.write(copyleft)
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f.write(copyleft)
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with open(infile) as g:
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with open(infile) as g:
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f.write(g.read())
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f.write(g.read())
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total += 1
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total += 1
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No newline at end of file
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No newline at end of file
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print ("All necessary A-Z80 CPU files are copied to", dest)
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print ("Add all Verilog files (*.v) to your project and ensure that Verilog include")
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print ("files (*.vh) are on the include path.\n")
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print ("Use z80_top_direct_n.v as your top-level interface file.\n")
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print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
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print ("copy and use data_pins_lattice.v file instead.")
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No newline at end of file
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No newline at end of file
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