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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Tue Mar 08 20:46:27 2016"
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// CREATED "Thu Dec 08 22:19:25 2016"
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module reg_control(
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module reg_control(
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ctl_reg_exx,
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ctl_reg_exx,
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ctl_reg_ex_af,
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ctl_reg_ex_af,
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ctl_reg_ex_de_hl,
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ctl_reg_ex_de_hl,
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| Line 32... |
Line 32... |
ctl_reg_sys_we_lo,
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ctl_reg_sys_we_lo,
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ctl_reg_sys_we_hi,
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ctl_reg_sys_we_hi,
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ctl_reg_sys_we,
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ctl_reg_sys_we,
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clk,
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clk,
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ctl_sw_4d,
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ctl_sw_4d,
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hold_clk_wait,
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ctl_reg_gp_hilo,
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ctl_reg_gp_hilo,
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ctl_reg_gp_sel,
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ctl_reg_gp_sel,
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ctl_reg_sys_hilo,
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ctl_reg_sys_hilo,
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reg_sel_bc,
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reg_sel_bc,
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reg_sel_bc2,
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reg_sel_bc2,
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| Line 78... |
Line 79... |
input wire ctl_reg_sys_we_lo;
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input wire ctl_reg_sys_we_lo;
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input wire ctl_reg_sys_we_hi;
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input wire ctl_reg_sys_we_hi;
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input wire ctl_reg_sys_we;
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input wire ctl_reg_sys_we;
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input wire clk;
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input wire clk;
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input wire ctl_sw_4d;
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input wire ctl_sw_4d;
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input wire hold_clk_wait;
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input wire [1:0] ctl_reg_gp_hilo;
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input wire [1:0] ctl_reg_gp_hilo;
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input wire [1:0] ctl_reg_gp_sel;
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input wire [1:0] ctl_reg_gp_sel;
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input wire [1:0] ctl_reg_sys_hilo;
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input wire [1:0] ctl_reg_sys_hilo;
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output wire reg_sel_bc;
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output wire reg_sel_bc;
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output wire reg_sel_bc2;
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output wire reg_sel_bc2;
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| Line 109... |
Line 111... |
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reg bank_af;
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reg bank_af;
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reg bank_exx;
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reg bank_exx;
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reg bank_hl_de1;
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reg bank_hl_de1;
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reg bank_hl_de2;
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reg bank_hl_de2;
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wire n_hold_clk_wait;
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wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
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wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
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wire SYNTHESIZED_WIRE_52;
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wire SYNTHESIZED_WIRE_52;
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wire SYNTHESIZED_WIRE_53;
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wire SYNTHESIZED_WIRE_53;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_54;
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wire SYNTHESIZED_WIRE_54;
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| Line 170... |
Line 173... |
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assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp;
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assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp;
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assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
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assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
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assign SYNTHESIZED_WIRE_37 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
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assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
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assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
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assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
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assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
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assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
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assign SYNTHESIZED_WIRE_2 = ~bank_af;
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assign SYNTHESIZED_WIRE_2 = ~bank_af;
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assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_47 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_41 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_50 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_49 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
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assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
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assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
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assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
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assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
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assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
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assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
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assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
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assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
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assign SYNTHESIZED_WIRE_40 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_53 = ~bank_exx;
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assign SYNTHESIZED_WIRE_53 = ~bank_exx;
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assign SYNTHESIZED_WIRE_46 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
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assign SYNTHESIZED_WIRE_45 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
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assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
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assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
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assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1;
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assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1;
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| Line 222... |
Line 225... |
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assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
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assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
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assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
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assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
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assign SYNTHESIZED_WIRE_44 = ~ctl_reg_gp_sel[0];
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assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];
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assign SYNTHESIZED_WIRE_39 = ctl_reg_ex_de_hl & bank_exx;
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assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
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assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
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assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
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assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
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assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
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assign SYNTHESIZED_WIRE_10 = ~use_ix;
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assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
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assign SYNTHESIZED_WIRE_43 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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bank_hl_de1 <= 0;
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bank_af <= 0;
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end
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end
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else
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else
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bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_37;
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if (n_hold_clk_wait)
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begin
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bank_af <= bank_af ^ ctl_reg_ex_af;
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end
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end
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end
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assign SYNTHESIZED_WIRE_10 = ~use_ix;
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assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
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assign SYNTHESIZED_WIRE_42 = ~SYNTHESIZED_WIRE_38;
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assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
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assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;
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assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
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assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
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assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
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assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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bank_hl_de2 <= 0;
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bank_hl_de2 <= 0;
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end
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end
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else
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else
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bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_39;
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if (n_hold_clk_wait)
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begin
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bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
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end
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end
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end
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assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_40 | SYNTHESIZED_WIRE_41;
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assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
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assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_42;
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assign SYNTHESIZED_WIRE_38 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_43 & ctl_reg_sel_ir;
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assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_44 & ctl_reg_gp_sel[1];
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assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_45 | SYNTHESIZED_WIRE_46;
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assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_47 | SYNTHESIZED_WIRE_48;
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assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_49 | SYNTHESIZED_WIRE_50;
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assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
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assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
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assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
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assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
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assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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bank_exx <= 0;
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bank_hl_de1 <= 0;
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end
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end
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else
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else
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bank_exx <= bank_exx ^ ctl_reg_exx;
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if (n_hold_clk_wait)
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begin
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bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
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end
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end
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end
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assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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bank_af <= 0;
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bank_exx <= 0;
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end
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end
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else
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else
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bank_af <= bank_af ^ ctl_reg_ex_af;
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if (n_hold_clk_wait)
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begin
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bank_exx <= bank_exx ^ ctl_reg_exx;
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end
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end
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end
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assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
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assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
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assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
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assign n_hold_clk_wait = ~hold_clk_wait;
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assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
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assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
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assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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