| Line 28... |
Line 28... |
reg [7:0] db_hi_ds; // Drive it using this bus
|
reg [7:0] db_hi_ds; // Drive it using this bus
|
wire [7:0] db_hi_ds_sig; // Read it using this bus
|
wire [7:0] db_hi_ds_sig; // Read it using this bus
|
|
|
// ----------------- CONTROL -----------------
|
// ----------------- CONTROL -----------------
|
reg ctl_sw_4u_sig; // Bus switch #4 upstream gate
|
reg ctl_sw_4u_sig; // Bus switch #4 upstream gate
|
reg ctl_sw_4d_sig; // Bus switch #4 downstream gate
|
reg reg_sw_4d_lo_sig; // Bus switch #4 downstream gate low byte lane
|
|
reg reg_sw_4d_hi_sig; // Bus switch #4 downstream gate high byte lane
|
|
|
// ----------------- GP REGS -----------------
|
// ----------------- GP REGS -----------------
|
reg reg_sel_af_sig; // Select AF register
|
reg reg_sel_af_sig; // Select AF register
|
reg reg_sel_af2_sig; // ...
|
reg reg_sel_af2_sig; // ...
|
reg reg_sel_bc_sig;
|
reg reg_sel_bc_sig;
|
| Line 61... |
Line 62... |
// ----------------- TEST -------------------
|
// ----------------- TEST -------------------
|
`define CHECK(arg) \
|
`define CHECK(arg) \
|
assert(db_sig===arg);
|
assert(db_sig===arg);
|
|
|
initial begin
|
initial begin
|
ctl_sw_4d_sig = 0;
|
reg_sw_4d_lo_sig = 0;
|
|
reg_sw_4d_hi_sig = 0;
|
ctl_sw_4u_sig = 0;
|
ctl_sw_4u_sig = 0;
|
|
|
reg_sel_af_sig = 0; // Select AF register
|
reg_sel_af_sig = 0; // Select AF register
|
reg_sel_af2_sig = 0; // ...
|
reg_sel_af2_sig = 0; // ...
|
reg_sel_bc_sig = 0;
|
reg_sel_bc_sig = 0;
|
| Line 137... |
Line 139... |
.reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig
|
.reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig
|
.reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig
|
.reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig
|
.reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig
|
.reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig
|
.reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig
|
.reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig
|
.reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig
|
.reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig
|
.ctl_sw_4d(ctl_sw_4d_sig) , // input ctl_sw_4d_sig
|
.reg_sw_4d_lo(reg_sw_4d_lo_sig) , // input reg_sw_4d_lo_sig
|
|
.reg_sw_4d_hi(reg_sw_4d_hi_sig) , // input reg_sw_4d_hi_sig
|
.ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig
|
.ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig
|
.reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig
|
.reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig
|
.reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig
|
.reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig
|
.reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig
|
.reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig
|
.reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig
|
.reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig
|
