Subversion Repositories a-z80

This is a list of source files that are part of the top-level design.

This is a list of source files that are part of the top-level design.

It is read by various Python scripts for the top level integration and

It is read by various Python scripts for the top level integration and

synthesis. Every line that does not refer to a valid file is ignored.

synthesis. Every line that does not refer to a valid file is ignored.

------ Control block -------

------ Control block -------

control/clk_delay.v

control/clk_delay.v

control/decode_state.v

control/decode_state.v

control/execute.sv

control/execute.sv

control/interrupts.v

control/interrupts.v

control/ir.v

control/ir.v

control/pin_control.v

control/pin_control.v

control/pla_decode.sv

control/pla_decode.sv

control/resets.v

control/resets.v

control/memory_ifc.v

control/memory_ifc.v

control/sequencer.v

control/sequencer.v

---------- ALU -------------

---------- ALU -------------

alu/alu_control.v

alu/alu_control.v

alu/alu_select.v

alu/alu_select.v

alu/alu_flags.v

alu/alu_flags.v

alu/alu.v

alu/alu.v

------ Register file -------

------ Register file -------

registers/reg_file.v

registers/reg_file.v

registers/reg_control.v

registers/reg_control.v

------ Address latch -------

------ Address latch -------

bus/address_latch.v

bus/address_latch.v

bus/address_pins.v

bus/address_pins.v

--------- Misc bus ---------

--------- Misc bus ---------

bus/bus_control.v

bus/bus_control.v

bus/bus_switch.sv

bus/bus_switch.sv

------ I/O pin control -----

------ I/O pin control -----

bus/data_pins.v

bus/data_pins.v

bus/control_pins_n.v

bus/control_pins_n.v