| Line 21... |
Line 21... |
decode_state decode_state_(
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decode_state decode_state_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_clr (ctl_state_tbl_clr),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.ctl_state_alu (ctl_state_alu),
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.clk (clk),
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.clk (clk),
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.address_is_1 (address_is_1),
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.address_is_1 (address_is_1),
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.ctl_repeat_we (ctl_repeat_we),
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.ctl_repeat_we (ctl_repeat_we),
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.in_intr (in_intr),
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.in_intr (in_intr),
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.in_nmi (in_nmi),
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.in_nmi (in_nmi),
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.nreset (nreset),
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.nreset (nreset),
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.ctl_state_tbl_we (ctl_state_tbl_we),
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.hold_clk_wait (hold_clk_wait),
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.in_halt (in_halt),
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.in_halt (in_halt),
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.table_cb (table_cb),
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.table_cb (table_cb),
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.table_ed (table_ed),
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.table_ed (table_ed),
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.table_xx (table_xx),
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.table_xx (table_xx),
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.use_ix (use_ix),
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.use_ix (use_ix),
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| Line 46... |
Line 47... |
execute execute_(
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execute execute_(
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_iy_set (ctl_state_iy_set),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_ixiy_we (ctl_state_ixiy_we),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_halt_set (ctl_state_halt_set),
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.ctl_state_tbl_clr (ctl_state_tbl_clr),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
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.ctl_state_alu (ctl_state_alu),
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.ctl_state_alu (ctl_state_alu),
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.ctl_repeat_we (ctl_repeat_we),
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.ctl_repeat_we (ctl_repeat_we),
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.ctl_state_tbl_we (ctl_state_tbl_we),
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.ctl_iff1_iff2 (ctl_iff1_iff2),
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.ctl_iff1_iff2 (ctl_iff1_iff2),
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.ctl_iffx_we (ctl_iffx_we),
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.ctl_iffx_we (ctl_iffx_we),
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.ctl_iffx_bit (ctl_iffx_bit),
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.ctl_iffx_bit (ctl_iffx_bit),
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.ctl_im_we (ctl_im_we),
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.ctl_im_we (ctl_im_we),
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.ctl_no_ints (ctl_no_ints),
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.ctl_no_ints (ctl_no_ints),
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| Line 198... |
Line 199... |
|
|
ir ir_(
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ir ir_(
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.ctl_ir_we (ctl_ir_we),
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.ctl_ir_we (ctl_ir_we),
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.clk (clk),
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.clk (clk),
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.nreset (nreset),
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.nreset (nreset),
|
|
.hold_clk_wait (hold_clk_wait),
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.db (db0[7:0]),
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.db (db0[7:0]),
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.opcode (opcode)
|
.opcode (opcode)
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);
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);
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|
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pin_control pin_control_(
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pin_control pin_control_(
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| Line 229... |
Line 231... |
.reset_in (reset_in),
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.reset_in (reset_in),
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.clk (clk),
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.clk (clk),
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.M1 (M1),
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.M1 (M1),
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.T2 (T2),
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.T2 (T2),
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.fpga_reset (fpga_reset),
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.fpga_reset (fpga_reset),
|
|
.hold_clk_wait (hold_clk_wait),
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.clrpc (clrpc),
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.clrpc (clrpc),
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.nreset (nreset)
|
.nreset (nreset)
|
);
|
);
|
|
|
memory_ifc memory_ifc_(
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memory_ifc memory_ifc_(
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| Line 253... |
Line 256... |
.nRFSH_out (nRFSH_out),
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.nRFSH_out (nRFSH_out),
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.nMREQ_out (nMREQ_out),
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.nMREQ_out (nMREQ_out),
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.nRD_out (nRD_out),
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.nRD_out (nRD_out),
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.nWR_out (nWR_out),
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.nWR_out (nWR_out),
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.nIORQ_out (nIORQ_out),
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.nIORQ_out (nIORQ_out),
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.latch_wait (latch_wait)
|
.latch_wait (latch_wait),
|
|
.wait_m1 (wait_m1)
|
);
|
);
|
|
|
sequencer sequencer_(
|
sequencer sequencer_(
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.clk (clk),
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.clk (clk),
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.nextM (nextM),
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.nextM (nextM),
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| Line 493... |
Line 497... |
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
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.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
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.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
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.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
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.ctl_reg_sys_we (ctl_reg_sys_we),
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.ctl_reg_sys_we (ctl_reg_sys_we),
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.clk (clk),
|
.clk (clk),
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.ctl_sw_4d (ctl_sw_4d),
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.ctl_sw_4d (ctl_sw_4d),
|
|
.hold_clk_wait (hold_clk_wait),
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.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
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.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
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.ctl_reg_gp_sel (ctl_reg_gp_sel),
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.ctl_reg_gp_sel (ctl_reg_gp_sel),
|
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
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.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
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.reg_sel_bc (reg_sel_bc),
|
.reg_sel_bc (reg_sel_bc),
|
.reg_sel_bc2 (reg_sel_bc2),
|
.reg_sel_bc2 (reg_sel_bc2),
|
