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Line 1... |
#!/usr/bin/env python
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#!/usr/bin/env python3
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#
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#
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# This script reads and parses selected Verilog and SystemVerilog modules
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# This script reads and parses selected Verilog and SystemVerilog modules
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# and generates a set of Verilog include files for the Z80 top-level block.
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# and generates a set of Verilog include files for the Z80 top-level block.
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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| Line 34... |
Line 34... |
if not os.path.isfile('../' + infile):
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if not os.path.isfile('../' + infile):
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continue
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continue
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with open('../' + infile, "r") as f:
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with open('../' + infile, "r") as f:
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for line in f:
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for line in f:
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info = line.split()
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info = line.split()
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if (len(info)>2):
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if len(info)>2:
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# There can be only one driver for each signal so we read only the outputs
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# There can be only one driver for each signal so we read only the outputs
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if (info[0]=="output") and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
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if info[0]=="output" and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
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# There are 2 cases: wires and buses
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# There are 2 cases: wires and buses
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if info[2].startswith('['):
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if info[2].startswith('['):
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wires.append(info[2] + ' ' + info[3].translate(None, ';,'))
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wires.append(info[2] + ' ' + info[3].strip(';,'))
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else:
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else:
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wires.append(info[2].translate(None, ';,'))
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wires.append(info[2].strip(';,'))
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if len(wires)>0:
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if len(wires)>0:
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with open('globals.vh', 'a') as file1:
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with open('globals.vh', 'a') as file1:
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file1.write("\n// Module: " + infile + "\n")
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file1.write("\n// Module: " + infile + "\n")
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for wire in wires:
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for wire in wires:
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| Line 57... |
Line 57... |
file1.write("wire " + wire + ";\n")
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file1.write("wire " + wire + ";\n")
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globals.append(wire)
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globals.append(wire)
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# Touch files that include 'globals.vh' to ensure it will recompile correctly
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# Touch files that include 'globals.vh' to ensure it will recompile correctly
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os.utime("core.vh", None)
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os.utime("core.vh", None)
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os.utime("z80_top_direct_n.sv", None)
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os.utime("z80_top_direct_n.v", None)
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os.utime("z80_top_ifc_n.sv", None)
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os.utime("z80_top_ifc_n.sv", None)
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No newline at end of file
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No newline at end of file
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