| Line 37... |
Line 37... |
wire nWR;
|
wire nWR;
|
wire nRFSH;
|
wire nRFSH;
|
wire nHALT;
|
wire nHALT;
|
wire nBUSACK;
|
wire nBUSACK;
|
|
|
wire nWAIT = 1;
|
wire nWAIT;
|
wire nINT = nint;
|
wire nINT = nint;
|
wire nNMI = nnmi;
|
wire nNMI = nnmi;
|
wire nBUSRQ = 1;
|
wire nBUSRQ = 1;
|
|
|
wire [15:0] A;
|
wire [15:0] A;
|
wire [7:0] D;
|
wire [7:0] D;
|
|
|
|
// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual
|
|
reg nWAIT_M1_sig;
|
|
reg nWAIT_Mem_sig;
|
|
|
|
// *** Uncomment one of the following 3 choices ***:
|
|
//assign nWAIT = nWAIT_M1_sig; // Add one wait state to an M1 cycle
|
|
//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)
|
|
assign nWAIT = 1; // Do not add wait cycles
|
|
|
// ----------------- INTERNAL WIRES -----------------
|
// ----------------- INTERNAL WIRES -----------------
|
wire [7:0] RamData; // RamData is a data writer from the RAM module
|
wire [7:0] RamData; // RamData is a data writer from the RAM module
|
wire RamWE;
|
wire RamWE;
|
assign RamWE = nIORQ==1 && nRD==1 && nWR==0;
|
assign RamWE = nIORQ==1 && nRD==1 && nWR==0;
|
|
|
| Line 66... |
Line 75... |
// Instantiate A-Z80 CPU module
|
// Instantiate A-Z80 CPU module
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk) );
|
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk) );
|
|
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)
|
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
wait_state wait_state_inst
|
|
(
|
|
.CLK(clk),
|
|
.nM1(nM1),
|
|
.nMREQ((nMREQ === z) ? 1'b1 : nMREQ), // Correct nMREQ from being tri-stated after reset
|
|
.nWAIT_M1(nWAIT_M1_sig),
|
|
.nWAIT_Mem(nWAIT_Mem_sig)
|
|
);
|
|
|
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
// Instantiate 16Kb of RAM memory
|
// Instantiate 16Kb of RAM memory
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
ram ram_( .address(A[13:0]), .clock(clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
|
ram ram_( .address(A[13:0]), .clock(clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
|
|
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
