URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [host/] [common/] [uart.v] - Diff between revs 14 and 17

Rev 14	Rev 17
Line 1...	Line 1...
`// Simple transmit-only UART model`	`// Simple transmit-only UART model`

`module uart #(`	`module uart #(`
`parameter BAUD = 115200,`	`parameter [28:0] BAUD = 115200,`
`parameter IN_CLOCK = 50000000)`	`parameter [28:0] IN_CLOCK = 50000000)`
`(`	`(`
`// Outputs`	`// Outputs`
`output wire busy, // Set when busy transmitting`	`output wire busy, // Set when busy transmitting`
`output reg uart_tx, // UART transmit wire`	`output reg uart_tx, // UART transmit wire`
`// Inputs`	`// Inputs`
Line 20...	Line 20...
`assign busy = \|bitcount[3:1];`	`assign busy = \|bitcount[3:1];`
`wire sending = \|bitcount;`	`wire sending = \|bitcount;`

`// Calculate UART clock based on the input clock`	`// Calculate UART clock based on the input clock`
`reg [28:0] d;`	`reg [28:0] d;`
`wire [28:0] inc = d[28] ? 29'(BAUD) : 29'(BAUD - IN_CLOCK);`	`wire [28:0] inc = d[28] ? (BAUD) : (BAUD - IN_CLOCK);`
`wire [28:0] delta = d + inc;`	`wire [28:0] delta = d + inc;`

`always @(posedge clk)`	`always @(posedge clk)`
`begin`	`begin`
`if (reset)`	`if (reset)`