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A-Z80
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A-Z80
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A conceptual implementation of the Z80 CPU
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A conceptual implementation of the Z80 CPU
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for Altera and Xilinx FPGAs
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for Altera, Xilinx and Lattice FPGAs
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This project is described in more details at: www.baltazarstudios.com
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This project is described in more details at www.baltazarstudios.com
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Prerequisites:
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Prerequisites:
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* Altera Quartus and Modelsim (free web editions) OR
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* Altera Quartus and Modelsim (free web editions) OR
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* Xilinx ISE (free Webpack edition)
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* Xilinx ISE (free Webpack edition) OR
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* Lattice ICECube toolchain from Synopsis (Lattice tested by JuanS)
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* Python 3.5.x
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* Python 3.5.x
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A-Z80 "cpu" consists of several functional blocks and a top-level module:
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"cpu" folder contains A-Z80 CPU functional blocks and top-level modules:
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alu contains ALU block, ALU control and flags logic
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alu contains ALU block, ALU control and flags logic
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bus contains data bus switches, pin logic, address latch and the
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bus contains data bus switches, pin logic, address latch and the
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address incrementer
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address incrementer
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register contains CPU register file and the register control logic
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registers contains CPU register file and the register control logic
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control contains PLA, the sequencer and other control blocks
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control contains PLA, the sequencer and other control blocks
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toplevel A-Z80 top level core, interfaces and the test code
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toplevel A-Z80 top level core, interfaces and test code
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"host" integrates the A-Z80 into several complete top-level designs:
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When exporting CPU files to use in your own project, run "export.py" script.
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"basic" contains a simplified board consisting of A-Z80 CPU, memory
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and UART modules that can run small Z80 programs
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"zxspectrum" contains an implementation of the Sinclair ZX Spectrum
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You probably want to start by loading one of those designs.
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"host" folder integrates the A-Z80 CPU into several fully functional designs:
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"basic_de1" contains a simplified board consisting of A-Z80 CPU, memory
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and UART modules that can run small Z80 programs on Altera DE1
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"basic_nexys3" contains the same example project but for Xilinx Nexys3 board
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"zxspectrum_de1" contains an implementation of the Sinclair ZX Spectrum
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for Altera DE1 board
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"tools" contains various tools related to the project.
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You may want to start by loading one of those designs.
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"tools", "resources" contain various tools related to the project, reverse
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engineering Z80 and testing.
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Read the 'readme.txt' files in each of the folders for additional information.
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Read the 'readme.txt' files in each of the folders for additional information.
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Read 'Quick Start' and 'Users Guide' documents in the 'docs' folder.
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Read 'Quick Start' and 'Users Guide' documents in the 'docs' folder.
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A-Z80 Logic Design
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A-Z80 Logic Design
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Quartus projects are only used as containers for files within individual
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Quartus projects are only used as containers for files within individual
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modules; complete and working top-level solutions that use A-Z80 are in the
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modules; complete and working top-level solutions that use A-Z80 are in the
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"host" folder.
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"host" folder.
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Majority of sub-modules are designed in the Quartus schematic editor and then
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Majority of sub-modules are designed in the Quartus schematic editor and then
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exported to Verilog for simulation and top-level integration. If you decide
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exported to Verilog for simulation and top-level integration.
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to create a design using the A-Z80 CPU, you can either use schematic files
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(in Altera Quartus) or corresponding Verilog sources (for both Altera
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and Xilinx tools).
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Simulation
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Simulation
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==========
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==========
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Before you can load and simulate any module through Modelsim, you need to set up
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Before you can load and simulate any module through Modelsim, you need to set up
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the environment by running a Python script 'modelsim_setup.py'. The script creates
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the environment by running 'modelsim_setup.py'. The script creates relative file
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relative file path mapping to source files in all module project folders.
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path mapping to source files in all module project folders.
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Each functional block, including the top level, contains a Modelsim simulation
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Each functional block, including the top level, contains a Modelsim simulation
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profile: .//simulation/modelsim/test_.mpf
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profile: .//simulation/modelsim/test_.mpf
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After opening a Modelsim session, create a library and compile sources:
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After opening a Modelsim session, create a library and compile sources:
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ModelSim> vlib work
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ModelSim> vlib work
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Compile->Compile All
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Compile->Compile All
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Run a simulation through one of the defined configurations.
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Run a simulation through one of the defined configurations.
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If you get a message "Unable to compile", you likely forgot to run 'modelsim_setup.py'.
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If you get a message "Unable to compile", you likely forgot to run 'modelsim_setup.py'.
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Exit ModelSim, git revert changes to ".mpf" file, delete "work" folder and run
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Exit ModelSim, revert changes to ".mpf" file, delete "work" folder and run
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'modelsim_setup.py'. Rinse, repeat.
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'modelsim_setup.py'.
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Each project contains a set of predefined waveform scripts which you can
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Each project contains a set of predefined waveform scripts which you can
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load before running a simulation:
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load before running a simulation:
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.//simulation/modelsim/wave_.do
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.//simulation/modelsim/wave_.do
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