###############################################################################
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###############################################################################
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#
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#
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# Actual Synthesis Script
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# Actual Synthesis Script
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#
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#
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# This script does the actual synthesis
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# This script does the actual synthesis
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#
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#
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# Author: Rudolf Usselmann
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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# rudi@asics.ws
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#
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#
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# Revision:
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# Revision:
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# 3/7/01 RU Initial Sript
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# 3/7/01 RU Initial Sript
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#
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#
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#
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#
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###############################################################################
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###############################################################################
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# ==============================================
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# ==============================================
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# Setup Design Parameters
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# Setup Design Parameters
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source ../bin/design_spec.dc
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source ../bin/design_spec.dc
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# ==============================================
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# ==============================================
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# Setup Libraries
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# Setup Libraries
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source ../bin/lib_spec.dc
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source ../bin/lib_spec.dc
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# ==============================================
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# ==============================================
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# Setup File IO
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# Setup File IO
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set junk_file /dev/null
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set junk_file /dev/null
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append log_file ../log/$active_design "_cmp.log"
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append log_file ../log/$active_design "_cmp.log"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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append post_comp_db_file ../out/$design_name ".db"
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append post_comp_db_file ../out/$design_name ".db"
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append post_syn_verilog_file ../out/$design_name "_ps.v"
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append post_syn_verilog_file ../out/$design_name "_ps.v"
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sh rm -f $log_file
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sh rm -f $log_file
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# ==============================================
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# ==============================================
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# Setup Misc Variables
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# Setup Misc Variables
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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# ==============================================
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# ==============================================
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# Read Design
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# Read Design
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echo "+++++++++ Reading Design ..." >> $log_file
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echo "+++++++++ Reading Design ..." >> $log_file
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read_file $pre_comp_db_file >> $log_file
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read_file $pre_comp_db_file >> $log_file
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# ==============================================
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# ==============================================
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# Operating conditions
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# Operating conditions
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echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
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echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
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current_design $design_name
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current_design $design_name
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set_operating_conditions WORST >> $log_file
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set_operating_conditions WORST >> $log_file
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# ==============================================
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# ==============================================
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# Setup Clocks and Resets
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# Setup Clocks and Resets
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echo "+++++++++ Setting up Clocks ..." >> $log_file
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echo "+++++++++ Setting up Clocks ..." >> $log_file
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set_drive 0 [find port {*clk}]
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set_drive 0 [find port {*clk}]
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# !!! WISHBONE Clock !!!
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# !!! WISHBONE Clock !!!
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set clock_period 5
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set clock_period 5
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create_clock -period $clock_period clk
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create_clock -period $clock_period clk
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set_clock_skew -uncertainty 0.1 clk
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set_clock_skew -uncertainty 0.1 clk
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set_clock_transition 0.5 clk
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set_clock_transition 0.5 clk
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set_dont_touch_network clk
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set_dont_touch_network clk
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# !!! BIT Clock !!!
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# !!! BIT Clock !!!
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set clock_period 500
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set clock_period 500
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create_clock -period $clock_period bit_clk
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create_clock -period $clock_period bit_clk
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set_clock_skew -uncertainty 0.1 bit_clk
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set_clock_skew -uncertainty 0.1 bit_clk
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set_clock_transition 0.5 bit_clk
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set_clock_transition 0.5 bit_clk
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set_dont_touch_network bit_clk
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set_dont_touch_network bit_clk
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# !!! Reset !!!
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# !!! Reset !!!
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set_drive 0 [find port {rst*}]
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set_drive 0 [find port {rst*}]
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set_dont_touch_network [find port {rst*}]
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set_dont_touch_network [find port {rst*}]
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# ==============================================
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# ==============================================
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# Setup IOs
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# Setup IOs
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echo "+++++++++ Setting up IOs ..." >> $log_file
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echo "+++++++++ Setting up IOs ..." >> $log_file
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# Need to spell out external IOs
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# Need to spell out external IOs
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set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
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set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
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set_load 0.2 [all_outputs]
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set_load 0.2 [all_outputs]
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set_input_delay -max 1 -clock clk [all_inputs]
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set_input_delay -max 1 -clock clk [all_inputs]
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set_output_delay -max 1 -clock clk [all_outputs]
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set_output_delay -max 1 -clock clk [all_outputs]
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set_input_delay -max 1 -clock bit_clk sdata_in
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set_input_delay -max 1 -clock bit_clk sdata_in
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set_output_delay -max 1 -clock bit_clk sdata_out
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set_output_delay -max 1 -clock bit_clk sdata_out
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# ==============================================
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# ==============================================
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# Setup Area Constrains
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# Setup Area Constrains
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set_max_area 0.0
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set_max_area 0.0
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# ==============================================
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# ==============================================
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# Force Ultra
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# Force Ultra
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set_ultra_optimization -f
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set_ultra_optimization -f
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# ==============================================
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# ==============================================
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# Compile Design
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# Compile Design
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echo "+++++++++ Starting Compile ..." >> $log_file
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echo "+++++++++ Starting Compile ..." >> $log_file
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#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
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#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
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compile -map_effort low -area_effort low >> $log_file
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compile -map_effort low -area_effort low >> $log_file
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#compile -map_effort high -area_effort high -ungroup_all >> $log_file
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#compile -map_effort high -area_effort high -ungroup_all >> $log_file
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#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
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#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
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# ==============================================
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# ==============================================
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# Write Out the optimized design
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# Write Out the optimized design
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echo "+++++++++ Saving Optimized Design ..." >> $log_file
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echo "+++++++++ Saving Optimized Design ..." >> $log_file
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write_file -format verilog -output $post_syn_verilog_file
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write_file -format verilog -output $post_syn_verilog_file
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write_file -hierarchy -format db -output $post_comp_db_file
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write_file -hierarchy -format db -output $post_comp_db_file
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# ==============================================
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# ==============================================
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# Create Some Basic Reports
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# Create Some Basic Reports
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echo "+++++++++ Reporting Final Results ..." >> $log_file
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echo "+++++++++ Reporting Final Results ..." >> $log_file
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report_timing -nworst 10 >> $log_file
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report_timing -nworst 10 >> $log_file
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report_area >> $log_file
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report_area >> $log_file
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