| Line 24... |
Line 24... |
///////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_crc32.v,v $
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// $Log: adbg_crc32.v,v $
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// Revision 1.3 2011-10-24 02:25:11 natey
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// Removed extraneous '#1' delays, which were a holdover from the original
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// versions in the previous dbg_if core.
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//
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// Revision 1.2 2010-01-10 22:54:10 Nathan
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// Revision 1.2 2010-01-10 22:54:10 Nathan
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// Update copyright dates
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// Update copyright dates
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//
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//
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// Revision 1.1 2008/07/22 20:28:29 Nathan
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// Revision 1.1 2008/07/22 20:28:29 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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| Line 98... |
Line 102... |
assign new_crc[31] = data ^ crc[0];
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assign new_crc[31] = data ^ crc[0];
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if(rst)
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if(rst)
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crc[31:0] <= #1 32'hffffffff;
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crc[31:0] <= 32'hffffffff;
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else if(clr)
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else if(clr)
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crc[31:0] <= #1 32'hffffffff;
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crc[31:0] <= 32'hffffffff;
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else if(enable)
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else if(enable)
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crc[31:0] <= #1 new_crc;
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crc[31:0] <= new_crc;
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else if (shift)
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else if (shift)
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crc[31:0] <= #1 {1'b0, crc[31:1]};
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crc[31:0] <= {1'b0, crc[31:1]};
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end
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end
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//assign crc_match = (crc == 32'h0);
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//assign crc_match = (crc == 32'h0);
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assign crc_out = crc; //[31];
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assign crc_out = crc; //[31];
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