| Line 5... |
Line 5... |
//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// This file is part of the SoC Debug Interface. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Nathan Yawn (nyawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 - 2010 Authors ////
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//// Copyright (C) 2000 - 2011 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 38... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_or1k_status_reg.v,v $
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// $Log: adbg_or1k_status_reg.v,v $
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// Revision 1.3 2011-10-24 02:25:11 natey
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// Removed extraneous '#1' delays, which were a holdover from the original
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// versions in the previous dbg_if core.
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//
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// Revision 1.2 2010-01-10 22:54:10 Nathan
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// Revision 1.2 2010-01-10 22:54:10 Nathan
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// Update copyright dates
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// Update copyright dates
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//
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//
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// Revision 1.1 2008/07/22 20:28:31 Nathan
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// Revision 1.1 2008/07/22 20:28:31 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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| Line 100... |
Line 105... |
// signal, we insure that the CPU will remain in the stalled state until
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// signal, we insure that the CPU will remain in the stalled state until
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// the debug host can read the state.
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// the debug host can read the state.
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always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if(rst_i)
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if(rst_i)
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stall_bp <= #1 1'b0;
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stall_bp <= 1'b0;
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else if(bp_i)
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else if(bp_i)
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stall_bp <= #1 1'b1;
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stall_bp <= 1'b1;
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else if(stall_reg_cpu)
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else if(stall_reg_cpu)
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stall_bp <= #1 1'b0;
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stall_bp <= 1'b0;
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end
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end
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// Synchronizing
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// Synchronizing
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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stall_bp_csff <= #1 1'b0;
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stall_bp_csff <= 1'b0;
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stall_bp_tck <= #1 1'b0;
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stall_bp_tck <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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stall_bp_csff <= #1 stall_bp;
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stall_bp_csff <= stall_bp;
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stall_bp_tck <= #1 stall_bp_csff;
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stall_bp_tck <= stall_bp_csff;
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end
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end
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end
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end
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|
|
always @ (posedge cpu_clk_i or posedge rst_i)
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always @ (posedge cpu_clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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stall_reg_csff <= #1 1'b0;
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stall_reg_csff <= 1'b0;
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stall_reg_cpu <= #1 1'b0;
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stall_reg_cpu <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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stall_reg_csff <= #1 stall_reg;
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stall_reg_csff <= stall_reg;
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stall_reg_cpu <= #1 stall_reg_csff;
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stall_reg_cpu <= stall_reg_csff;
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end
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end
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end
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end
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|
|
// bp_i forces a stall immediately on a breakpoint
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// bp_i forces a stall immediately on a breakpoint
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// stall_bp holds the stall until the debug host acts
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// stall_bp holds the stall until the debug host acts
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| Line 150... |
Line 155... |
// This can be set either by the debug host, or by
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// This can be set either by the debug host, or by
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// a CPU breakpoint. It can only be cleared by the host.
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// a CPU breakpoint. It can only be cleared by the host.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
stall_reg <= #1 1'b0;
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stall_reg <= 1'b0;
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else if (stall_bp_tck)
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else if (stall_bp_tck)
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stall_reg <= #1 1'b1;
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stall_reg <= 1'b1;
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else if (we_i)
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else if (we_i)
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stall_reg <= #1 data_i[0];
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stall_reg <= data_i[0];
|
end
|
end
|
|
|
|
|
// Writing data to the control registers (reset)
|
// Writing data to the control registers (reset)
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
cpu_reset <= #1 1'b0;
|
cpu_reset <= 1'b0;
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else if(we_i)
|
else if(we_i)
|
cpu_reset <= #1 data_i[1];
|
cpu_reset <= data_i[1];
|
end
|
end
|
|
|
|
|
// Synchronizing signals from registers
|
// Synchronizing signals from registers
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
always @ (posedge cpu_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
cpu_reset_csff <= #1 1'b0;
|
cpu_reset_csff <= 1'b0;
|
cpu_rst_o <= #1 1'b0;
|
cpu_rst_o <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cpu_reset_csff <= #1 cpu_reset;
|
cpu_reset_csff <= cpu_reset;
|
cpu_rst_o <= #1 cpu_reset_csff;
|
cpu_rst_o <= cpu_reset_csff;
|
end
|
end
|
end
|
end
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