| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: tap_top.v,v $
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// $Log: tap_top.v,v $
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// Revision 1.6 2011-10-24 02:18:58 natey
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// Removed '#1' delays, which were a holdover from the original version. Ran
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// through dos2unix.
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//
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// Revision 1.5 2009-06-16 02:53:58 Nathan
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// Revision 1.5 2009-06-16 02:53:58 Nathan
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// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
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// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
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//
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//
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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| Line 360... |
Line 364... |
wire instruction_tdo;
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wire instruction_tdo;
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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begin
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begin
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if(trstn_pad_i == 0)
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if(trstn_pad_i == 0)
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jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
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jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
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else if (test_logic_reset == 1)
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else if (test_logic_reset == 1)
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jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
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jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
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else if(capture_ir)
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else if(capture_ir)
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jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
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jtag_ir <= 4'b0101; // This value is fixed for easier fault detection
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else if(shift_ir)
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else if(shift_ir)
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jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
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jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
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end
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end
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assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
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assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
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// Updating jtag_ir (Instruction Register)
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// Updating jtag_ir (Instruction Register)
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// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
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// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
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always @ (negedge tck_pad_i or negedge trstn_pad_i)
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always @ (negedge tck_pad_i or negedge trstn_pad_i)
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begin
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begin
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if(trstn_pad_i == 0)
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if(trstn_pad_i == 0)
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latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
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latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
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else if (test_logic_reset)
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else if (test_logic_reset)
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latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
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latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
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else if(update_ir)
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else if(update_ir)
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latched_jtag_ir <=#1 jtag_ir;
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latched_jtag_ir <= jtag_ir;
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end
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end
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* End: jtag_ir *
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* End: jtag_ir *
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| Line 402... |
Line 406... |
wire idcode_tdo;
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wire idcode_tdo;
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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begin
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begin
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if(trstn_pad_i == 0)
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if(trstn_pad_i == 0)
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idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
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idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
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else if (test_logic_reset)
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else if (test_logic_reset)
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idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
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idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
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else if(idcode_select & capture_dr)
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else if(idcode_select & capture_dr)
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idcode_reg <= #1 `IDCODE_VALUE;
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idcode_reg <= `IDCODE_VALUE;
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else if(idcode_select & shift_dr)
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else if(idcode_select & shift_dr)
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idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
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idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
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end
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end
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assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
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assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
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| Line 432... |
Line 436... |
reg bypass_reg; // This is a 1-bit register
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reg bypass_reg; // This is a 1-bit register
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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begin
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begin
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if (trstn_pad_i == 0)
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if (trstn_pad_i == 0)
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bypass_reg <= #1 1'b0;
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bypass_reg <= 1'b0;
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else if (test_logic_reset == 1)
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else if (test_logic_reset == 1)
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bypass_reg <= #1 1'b0;
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bypass_reg <= 1'b0;
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else if (bypass_select & capture_dr)
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else if (bypass_select & capture_dr)
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bypass_reg<=#1 1'b0;
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bypass_reg<= 1'b0;
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else if(bypass_select & shift_dr)
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else if(bypass_select & shift_dr)
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bypass_reg<=#1 tdi_pad_i;
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bypass_reg<= tdi_pad_i;
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end
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end
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assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
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assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
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/**********************************************************************************
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/**********************************************************************************
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| Line 513... |
Line 517... |
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// Tristate control for tdo_pad_o pin
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// Tristate control for tdo_pad_o pin
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always @ (posedge tck_pad_i)
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always @ (posedge tck_pad_i)
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begin
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begin
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tdo_padoe_o <= #1 shift_ir | shift_dr;
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tdo_padoe_o <= shift_ir | shift_dr;
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end
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end
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* End: Multiplexing TDO data *
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* End: Multiplexing TDO data *
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* *
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* *
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