//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tap_top.v ////
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//// tap_top.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the JTAG Test Access Port (TAP) ////
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//// This file is part of the JTAG Test Access Port (TAP) ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the jtag.pdf ////
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//// All additional information is avaliable in the jtag.pdf ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 - 2008 Authors ////
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//// Copyright (C) 2000 - 2008 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: tap_top.v,v $
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// $Log: tap_top.v,v $
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// Revision 1.6 2011-10-24 02:18:58 natey
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// Removed '#1' delays, which were a holdover from the original version. Ran
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// through dos2unix.
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//
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// Revision 1.5 2009-06-16 02:53:58 Nathan
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// Revision 1.5 2009-06-16 02:53:58 Nathan
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// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
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// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
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//
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//
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.3 2008/06/18 18:45:07 Nathan
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// Revision 1.3 2008/06/18 18:45:07 Nathan
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// Improved reset slightly. Cleanup.
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// Improved reset slightly. Cleanup.
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//
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//
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//
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//
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// Revision 1.2 2008/05/14 13:13:24 Nathan
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// Revision 1.2 2008/05/14 13:13:24 Nathan
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// Rewrote TAP FSM in canonical form, for readability. Switched
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// Rewrote TAP FSM in canonical form, for readability. Switched
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// from one-hot to binary encoding. Made reset signal active-
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// from one-hot to binary encoding. Made reset signal active-
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// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset
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// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset
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// done in Test Logic Reset mode. Added test_logic_reset_o and
|
// done in Test Logic Reset mode. Added test_logic_reset_o and
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// run_test_idle_o signals. Removed double registers from IR data
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// run_test_idle_o signals. Removed double registers from IR data
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// path. Unified the registers at the output of each data register
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// path. Unified the registers at the output of each data register
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// to a single shared FF.
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// to a single shared FF.
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//
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//
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`include "tap_defines.v"
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`include "tap_defines.v"
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// Top module
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// Top module
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module tap_top(
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module tap_top(
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// JTAG pads
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// JTAG pads
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tms_pad_i,
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tms_pad_i,
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tck_pad_i,
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tck_pad_i,
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trstn_pad_i,
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trstn_pad_i,
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tdi_pad_i,
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tdi_pad_i,
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tdo_pad_o,
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tdo_pad_o,
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tdo_padoe_o,
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tdo_padoe_o,
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// TAP states
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// TAP states
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test_logic_reset_o,
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test_logic_reset_o,
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run_test_idle_o,
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run_test_idle_o,
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shift_dr_o,
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shift_dr_o,
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pause_dr_o,
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pause_dr_o,
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update_dr_o,
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update_dr_o,
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capture_dr_o,
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capture_dr_o,
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|
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// Select signals for boundary scan or mbist
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// Select signals for boundary scan or mbist
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extest_select_o,
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extest_select_o,
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sample_preload_select_o,
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sample_preload_select_o,
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mbist_select_o,
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mbist_select_o,
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debug_select_o,
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debug_select_o,
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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tdi_o,
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tdi_o,
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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debug_tdo_i, // from debug module
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debug_tdo_i, // from debug module
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bs_chain_tdo_i, // from Boundary Scan Chain
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bs_chain_tdo_i, // from Boundary Scan Chain
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mbist_tdo_i // from Mbist Chain
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mbist_tdo_i // from Mbist Chain
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);
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);
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// JTAG pins
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// JTAG pins
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input tms_pad_i; // JTAG test mode select pad
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input tms_pad_i; // JTAG test mode select pad
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input tck_pad_i; // JTAG test clock pad
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input tck_pad_i; // JTAG test clock pad
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input trstn_pad_i; // JTAG test reset pad
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input trstn_pad_i; // JTAG test reset pad
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input tdi_pad_i; // JTAG test data input pad
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input tdi_pad_i; // JTAG test data input pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_padoe_o; // Output enable for JTAG test data output pad
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output tdo_padoe_o; // Output enable for JTAG test data output pad
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// TAP states
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// TAP states
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output test_logic_reset_o;
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output test_logic_reset_o;
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output run_test_idle_o;
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output run_test_idle_o;
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output shift_dr_o;
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output shift_dr_o;
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output pause_dr_o;
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output pause_dr_o;
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output update_dr_o;
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output update_dr_o;
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output capture_dr_o;
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output capture_dr_o;
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// Select signals for boundary scan or mbist
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// Select signals for boundary scan or mbist
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output extest_select_o;
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output extest_select_o;
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output sample_preload_select_o;
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output sample_preload_select_o;
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output mbist_select_o;
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output mbist_select_o;
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output debug_select_o;
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output debug_select_o;
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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output tdi_o;
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output tdi_o;
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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input debug_tdo_i; // from debug module
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input debug_tdo_i; // from debug module
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input bs_chain_tdo_i; // from Boundary Scan Chain
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input bs_chain_tdo_i; // from Boundary Scan Chain
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input mbist_tdo_i; // from Mbist Chain
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input mbist_tdo_i; // from Mbist Chain
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// Wires which depend on the state of the TAP FSM
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// Wires which depend on the state of the TAP FSM
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reg test_logic_reset;
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reg test_logic_reset;
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reg run_test_idle;
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reg run_test_idle;
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reg select_dr_scan;
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reg select_dr_scan;
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reg capture_dr;
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reg capture_dr;
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reg shift_dr;
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reg shift_dr;
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reg exit1_dr;
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reg exit1_dr;
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reg pause_dr;
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reg pause_dr;
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reg exit2_dr;
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reg exit2_dr;
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reg update_dr;
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reg update_dr;
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reg select_ir_scan;
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reg select_ir_scan;
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reg capture_ir;
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reg capture_ir;
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reg shift_ir;
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reg shift_ir;
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reg exit1_ir;
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reg exit1_ir;
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reg pause_ir;
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reg pause_ir;
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reg exit2_ir;
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reg exit2_ir;
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reg update_ir;
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reg update_ir;
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// Wires which depend on the current value in the IR
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// Wires which depend on the current value in the IR
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reg extest_select;
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reg extest_select;
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reg sample_preload_select;
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reg sample_preload_select;
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reg idcode_select;
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reg idcode_select;
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reg mbist_select;
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reg mbist_select;
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reg debug_select;
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reg debug_select;
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reg bypass_select;
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reg bypass_select;
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// TDO and enable
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// TDO and enable
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reg tdo_pad_o;
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reg tdo_pad_o;
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reg tdo_padoe_o;
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reg tdo_padoe_o;
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|
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assign tdi_o = tdi_pad_i;
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assign tdi_o = tdi_pad_i;
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assign test_logic_reset_o = test_logic_reset;
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assign test_logic_reset_o = test_logic_reset;
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assign run_test_idle_o = run_test_idle;
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assign run_test_idle_o = run_test_idle;
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assign shift_dr_o = shift_dr;
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assign shift_dr_o = shift_dr;
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assign pause_dr_o = pause_dr;
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assign pause_dr_o = pause_dr;
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assign update_dr_o = update_dr;
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assign update_dr_o = update_dr;
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assign capture_dr_o = capture_dr;
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assign capture_dr_o = capture_dr;
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assign extest_select_o = extest_select;
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assign extest_select_o = extest_select;
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assign sample_preload_select_o = sample_preload_select;
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assign sample_preload_select_o = sample_preload_select;
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assign mbist_select_o = mbist_select;
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assign mbist_select_o = mbist_select;
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assign debug_select_o = debug_select;
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assign debug_select_o = debug_select;
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|
|
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* TAP State Machine: Fully JTAG compliant *
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* TAP State Machine: Fully JTAG compliant *
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* *
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* *
|
**********************************************************************************/
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**********************************************************************************/
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// Definition of machine state values. We could one-hot encode this, and use 16
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// Definition of machine state values. We could one-hot encode this, and use 16
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// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
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// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
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`define STATE_test_logic_reset 4'hF
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`define STATE_test_logic_reset 4'hF
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`define STATE_run_test_idle 4'hC
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`define STATE_run_test_idle 4'hC
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`define STATE_select_dr_scan 4'h7
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`define STATE_select_dr_scan 4'h7
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`define STATE_capture_dr 4'h6
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`define STATE_capture_dr 4'h6
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`define STATE_shift_dr 4'h2
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`define STATE_shift_dr 4'h2
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`define STATE_exit1_dr 4'h1
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`define STATE_exit1_dr 4'h1
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`define STATE_pause_dr 4'h3
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`define STATE_pause_dr 4'h3
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`define STATE_exit2_dr 4'h0
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`define STATE_exit2_dr 4'h0
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`define STATE_update_dr 4'h5
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`define STATE_update_dr 4'h5
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`define STATE_select_ir_scan 4'h4
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`define STATE_select_ir_scan 4'h4
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`define STATE_capture_ir 4'hE
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`define STATE_capture_ir 4'hE
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`define STATE_shift_ir 4'hA
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`define STATE_shift_ir 4'hA
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`define STATE_exit1_ir 4'h9
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`define STATE_exit1_ir 4'h9
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`define STATE_pause_ir 4'hB
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`define STATE_pause_ir 4'hB
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`define STATE_exit2_ir 4'h8
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`define STATE_exit2_ir 4'h8
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`define STATE_update_ir 4'hD
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`define STATE_update_ir 4'hD
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|
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reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
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reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
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reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal
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reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal
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// sequential part of the FSM
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// sequential part of the FSM
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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always @ (posedge tck_pad_i or negedge trstn_pad_i)
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begin
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begin
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if(trstn_pad_i == 0)
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if(trstn_pad_i == 0)
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TAP_state = `STATE_test_logic_reset;
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TAP_state = `STATE_test_logic_reset;
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else
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else
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TAP_state = next_TAP_state;
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TAP_state = next_TAP_state;
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end
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end
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|
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// Determination of next state; purely combinatorial
|
// Determination of next state; purely combinatorial
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always @ (TAP_state or tms_pad_i)
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always @ (TAP_state or tms_pad_i)
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begin
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begin
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case(TAP_state)
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case(TAP_state)
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`STATE_test_logic_reset:
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`STATE_test_logic_reset:
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begin
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begin
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if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
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if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
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else next_TAP_state = `STATE_run_test_idle;
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else next_TAP_state = `STATE_run_test_idle;
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end
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end
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`STATE_run_test_idle:
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`STATE_run_test_idle:
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begin
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begin
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if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
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if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
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else next_TAP_state = `STATE_run_test_idle;
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else next_TAP_state = `STATE_run_test_idle;
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end
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end
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`STATE_select_dr_scan:
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`STATE_select_dr_scan:
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begin
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begin
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if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
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if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
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else next_TAP_state = `STATE_capture_dr;
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else next_TAP_state = `STATE_capture_dr;
|
end
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end
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`STATE_capture_dr:
|
`STATE_capture_dr:
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begin
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begin
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if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
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if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
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else next_TAP_state = `STATE_shift_dr;
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else next_TAP_state = `STATE_shift_dr;
|
end
|
end
|
`STATE_shift_dr:
|
`STATE_shift_dr:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
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if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
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else next_TAP_state = `STATE_shift_dr;
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else next_TAP_state = `STATE_shift_dr;
|
end
|
end
|
`STATE_exit1_dr:
|
`STATE_exit1_dr:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
|
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
|
else next_TAP_state = `STATE_pause_dr;
|
else next_TAP_state = `STATE_pause_dr;
|
end
|
end
|
`STATE_pause_dr:
|
`STATE_pause_dr:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
|
if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
|
else next_TAP_state = `STATE_pause_dr;
|
else next_TAP_state = `STATE_pause_dr;
|
end
|
end
|
`STATE_exit2_dr:
|
`STATE_exit2_dr:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
|
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
|
else next_TAP_state = `STATE_shift_dr;
|
else next_TAP_state = `STATE_shift_dr;
|
end
|
end
|
`STATE_update_dr:
|
`STATE_update_dr:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
|
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
|
else next_TAP_state = `STATE_run_test_idle;
|
else next_TAP_state = `STATE_run_test_idle;
|
end
|
end
|
`STATE_select_ir_scan:
|
`STATE_select_ir_scan:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
|
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
|
else next_TAP_state = `STATE_capture_ir;
|
else next_TAP_state = `STATE_capture_ir;
|
end
|
end
|
`STATE_capture_ir:
|
`STATE_capture_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
|
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
end
|
end
|
`STATE_shift_ir:
|
`STATE_shift_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
|
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
end
|
end
|
`STATE_exit1_ir:
|
`STATE_exit1_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
|
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
|
else next_TAP_state = `STATE_pause_ir;
|
else next_TAP_state = `STATE_pause_ir;
|
end
|
end
|
`STATE_pause_ir:
|
`STATE_pause_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
|
if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
|
else next_TAP_state = `STATE_pause_ir;
|
else next_TAP_state = `STATE_pause_ir;
|
end
|
end
|
`STATE_exit2_ir:
|
`STATE_exit2_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
|
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
else next_TAP_state = `STATE_shift_ir;
|
end
|
end
|
`STATE_update_ir:
|
`STATE_update_ir:
|
begin
|
begin
|
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
|
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
|
else next_TAP_state = `STATE_run_test_idle;
|
else next_TAP_state = `STATE_run_test_idle;
|
end
|
end
|
default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
|
default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// Outputs of state machine, pure combinatorial
|
// Outputs of state machine, pure combinatorial
|
always @ (TAP_state)
|
always @ (TAP_state)
|
begin
|
begin
|
// Default everything to 0, keeps the case statement simple
|
// Default everything to 0, keeps the case statement simple
|
test_logic_reset = 1'b0;
|
test_logic_reset = 1'b0;
|
run_test_idle = 1'b0;
|
run_test_idle = 1'b0;
|
select_dr_scan = 1'b0;
|
select_dr_scan = 1'b0;
|
capture_dr = 1'b0;
|
capture_dr = 1'b0;
|
shift_dr = 1'b0;
|
shift_dr = 1'b0;
|
exit1_dr = 1'b0;
|
exit1_dr = 1'b0;
|
pause_dr = 1'b0;
|
pause_dr = 1'b0;
|
exit2_dr = 1'b0;
|
exit2_dr = 1'b0;
|
update_dr = 1'b0;
|
update_dr = 1'b0;
|
select_ir_scan = 1'b0;
|
select_ir_scan = 1'b0;
|
capture_ir = 1'b0;
|
capture_ir = 1'b0;
|
shift_ir = 1'b0;
|
shift_ir = 1'b0;
|
exit1_ir = 1'b0;
|
exit1_ir = 1'b0;
|
pause_ir = 1'b0;
|
pause_ir = 1'b0;
|
exit2_ir = 1'b0;
|
exit2_ir = 1'b0;
|
update_ir = 1'b0;
|
update_ir = 1'b0;
|
|
|
case(TAP_state)
|
case(TAP_state)
|
`STATE_test_logic_reset: test_logic_reset = 1'b1;
|
`STATE_test_logic_reset: test_logic_reset = 1'b1;
|
`STATE_run_test_idle: run_test_idle = 1'b1;
|
`STATE_run_test_idle: run_test_idle = 1'b1;
|
`STATE_select_dr_scan: select_dr_scan = 1'b1;
|
`STATE_select_dr_scan: select_dr_scan = 1'b1;
|
`STATE_capture_dr: capture_dr = 1'b1;
|
`STATE_capture_dr: capture_dr = 1'b1;
|
`STATE_shift_dr: shift_dr = 1'b1;
|
`STATE_shift_dr: shift_dr = 1'b1;
|
`STATE_exit1_dr: exit1_dr = 1'b1;
|
`STATE_exit1_dr: exit1_dr = 1'b1;
|
`STATE_pause_dr: pause_dr = 1'b1;
|
`STATE_pause_dr: pause_dr = 1'b1;
|
`STATE_exit2_dr: exit2_dr = 1'b1;
|
`STATE_exit2_dr: exit2_dr = 1'b1;
|
`STATE_update_dr: update_dr = 1'b1;
|
`STATE_update_dr: update_dr = 1'b1;
|
`STATE_select_ir_scan: select_ir_scan = 1'b1;
|
`STATE_select_ir_scan: select_ir_scan = 1'b1;
|
`STATE_capture_ir: capture_ir = 1'b1;
|
`STATE_capture_ir: capture_ir = 1'b1;
|
`STATE_shift_ir: shift_ir = 1'b1;
|
`STATE_shift_ir: shift_ir = 1'b1;
|
`STATE_exit1_ir: exit1_ir = 1'b1;
|
`STATE_exit1_ir: exit1_ir = 1'b1;
|
`STATE_pause_ir: pause_ir = 1'b1;
|
`STATE_pause_ir: pause_ir = 1'b1;
|
`STATE_exit2_ir: exit2_ir = 1'b1;
|
`STATE_exit2_ir: exit2_ir = 1'b1;
|
`STATE_update_ir: update_ir = 1'b1;
|
`STATE_update_ir: update_ir = 1'b1;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: TAP State Machine *
|
* End: TAP State Machine *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* jtag_ir: JTAG Instruction Register *
|
* jtag_ir: JTAG Instruction Register *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
|
reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
|
reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
|
reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
|
wire instruction_tdo;
|
wire instruction_tdo;
|
|
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
begin
|
begin
|
if(trstn_pad_i == 0)
|
if(trstn_pad_i == 0)
|
jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
|
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
|
else if (test_logic_reset == 1)
|
else if (test_logic_reset == 1)
|
jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
|
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
|
else if(capture_ir)
|
else if(capture_ir)
|
jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection
|
jtag_ir <= 4'b0101; // This value is fixed for easier fault detection
|
else if(shift_ir)
|
else if(shift_ir)
|
jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
|
jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
|
end
|
end
|
|
|
assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
|
assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
|
|
|
// Updating jtag_ir (Instruction Register)
|
// Updating jtag_ir (Instruction Register)
|
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
|
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
|
always @ (negedge tck_pad_i or negedge trstn_pad_i)
|
always @ (negedge tck_pad_i or negedge trstn_pad_i)
|
begin
|
begin
|
if(trstn_pad_i == 0)
|
if(trstn_pad_i == 0)
|
latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
|
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
|
else if (test_logic_reset)
|
else if (test_logic_reset)
|
latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
|
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
|
else if(update_ir)
|
else if(update_ir)
|
latched_jtag_ir <=#1 jtag_ir;
|
latched_jtag_ir <= jtag_ir;
|
end
|
end
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: jtag_ir *
|
* End: jtag_ir *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* idcode logic *
|
* idcode logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg [31:0] idcode_reg;
|
reg [31:0] idcode_reg;
|
wire idcode_tdo;
|
wire idcode_tdo;
|
|
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
begin
|
begin
|
if(trstn_pad_i == 0)
|
if(trstn_pad_i == 0)
|
idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
|
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
|
else if (test_logic_reset)
|
else if (test_logic_reset)
|
idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
|
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
|
else if(idcode_select & capture_dr)
|
else if(idcode_select & capture_dr)
|
idcode_reg <= #1 `IDCODE_VALUE;
|
idcode_reg <= `IDCODE_VALUE;
|
else if(idcode_select & shift_dr)
|
else if(idcode_select & shift_dr)
|
idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
|
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
|
|
|
end
|
end
|
|
|
assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
|
assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: idcode logic *
|
* End: idcode logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Bypass logic *
|
* Bypass logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
wire bypassed_tdo;
|
wire bypassed_tdo;
|
reg bypass_reg; // This is a 1-bit register
|
reg bypass_reg; // This is a 1-bit register
|
|
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
always @ (posedge tck_pad_i or negedge trstn_pad_i)
|
begin
|
begin
|
if (trstn_pad_i == 0)
|
if (trstn_pad_i == 0)
|
bypass_reg <= #1 1'b0;
|
bypass_reg <= 1'b0;
|
else if (test_logic_reset == 1)
|
else if (test_logic_reset == 1)
|
bypass_reg <= #1 1'b0;
|
bypass_reg <= 1'b0;
|
else if (bypass_select & capture_dr)
|
else if (bypass_select & capture_dr)
|
bypass_reg<=#1 1'b0;
|
bypass_reg<= 1'b0;
|
else if(bypass_select & shift_dr)
|
else if(bypass_select & shift_dr)
|
bypass_reg<=#1 tdi_pad_i;
|
bypass_reg<= tdi_pad_i;
|
end
|
end
|
|
|
assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
|
assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Bypass logic *
|
* End: Bypass logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Selecting active data register *
|
* Selecting active data register *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (latched_jtag_ir)
|
always @ (latched_jtag_ir)
|
begin
|
begin
|
extest_select = 1'b0;
|
extest_select = 1'b0;
|
sample_preload_select = 1'b0;
|
sample_preload_select = 1'b0;
|
idcode_select = 1'b0;
|
idcode_select = 1'b0;
|
mbist_select = 1'b0;
|
mbist_select = 1'b0;
|
debug_select = 1'b0;
|
debug_select = 1'b0;
|
bypass_select = 1'b0;
|
bypass_select = 1'b0;
|
|
|
case(latched_jtag_ir) /* synthesis parallel_case */
|
case(latched_jtag_ir) /* synthesis parallel_case */
|
`EXTEST: extest_select = 1'b1; // External test
|
`EXTEST: extest_select = 1'b1; // External test
|
`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
|
`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
|
`IDCODE: idcode_select = 1'b1; // ID Code
|
`IDCODE: idcode_select = 1'b1; // ID Code
|
`MBIST: mbist_select = 1'b1; // Mbist test
|
`MBIST: mbist_select = 1'b1; // Mbist test
|
`DEBUG: debug_select = 1'b1; // Debug
|
`DEBUG: debug_select = 1'b1; // Debug
|
`BYPASS: bypass_select = 1'b1; // BYPASS
|
`BYPASS: bypass_select = 1'b1; // BYPASS
|
default: bypass_select = 1'b1; // BYPASS
|
default: bypass_select = 1'b1; // BYPASS
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Multiplexing TDO data *
|
* Multiplexing TDO data *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
reg tdo_mux_out; // really just a wire
|
reg tdo_mux_out; // really just a wire
|
|
|
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
|
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
|
debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
|
debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
|
bs_chain_tdo_i)
|
bs_chain_tdo_i)
|
begin
|
begin
|
if(shift_ir)
|
if(shift_ir)
|
tdo_mux_out = instruction_tdo;
|
tdo_mux_out = instruction_tdo;
|
else
|
else
|
begin
|
begin
|
case(latched_jtag_ir) // synthesis parallel_case
|
case(latched_jtag_ir) // synthesis parallel_case
|
`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
|
`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
|
`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
|
`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
|
`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
|
`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
|
`EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test
|
`EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test
|
`MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test
|
`MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test
|
default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
|
default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
// TDO changes state at negative edge of TCK
|
// TDO changes state at negative edge of TCK
|
always @ (negedge tck_pad_i)
|
always @ (negedge tck_pad_i)
|
begin
|
begin
|
tdo_pad_o = tdo_mux_out;
|
tdo_pad_o = tdo_mux_out;
|
end
|
end
|
|
|
|
|
// Tristate control for tdo_pad_o pin
|
// Tristate control for tdo_pad_o pin
|
always @ (posedge tck_pad_i)
|
always @ (posedge tck_pad_i)
|
begin
|
begin
|
tdo_padoe_o <= #1 shift_ir | shift_dr;
|
tdo_padoe_o <= shift_ir | shift_dr;
|
end
|
end
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Multiplexing TDO data *
|
* End: Multiplexing TDO data *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
endmodule
|
endmodule
|
|
|