| Line 1... |
Line 1... |
----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Company: Czech Television
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-- AES3 / SPDIF Minimalistic Receiver
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-- Engineer: Petr Nohavica
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-- Version 0.9
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--
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-- Petr Nohavica (c) 2009
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-- Create Date: 09:02:45 05/09/2009
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-- Released under GNU Lesser General Public License
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-- Module Name: aes3rx - Behavioral
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-- Original target device: Xilinx Spartan-3AN family
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-- Project Name: AES3 minimalistic receiver
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-------------------------------------------------------------------------------
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-- Target Devices: Spartan 3
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|
-- Tool versions: ISE 10.1
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|
----------------------------------------------------------------------------------
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|
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|
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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|
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Library UNISIM;
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use UNISIM.vcomponents.all;
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|
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entity aes3rx is
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entity aes3rx is
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generic (
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generic (
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reg_width : integer := 4
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-- Registers width, determines minimal baud speed of input AES3 at given master clock frequency
|
|
reg_width : integer := 5
|
);
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);
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port (
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port (
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clk_in: in std_logic; -- master clock
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-- Master clock
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aes3 : in std_logic; -- input
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clk : in std_logic;
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reset : in std_logic; -- synchronous reset
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-- AES3/SPDIF compatible input signal
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aes3 : in std_logic;
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-- Synchronous reset
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reset : in std_logic;
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-- Serial data out
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sdata : out std_logic := '0'; -- output serial data
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sdata : out std_logic := '0'; -- output serial data
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-- AES3 clock out
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sclk : out std_logic := '0'; -- output serial data clock
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sclk : out std_logic := '0'; -- output serial data clock
|
bsync : out std_logic := '0'; -- block start (high when Z subframe is being transmitted)
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-- Block start (asserted when Z subframe is being transmitted)
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lrck : out std_logic := '0'; -- frame sync (high for channel A, low for B)
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bsync : out std_logic := '0';
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active: out std_logic := '0' -- receiver has valid data on its outputs
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-- Frame sync (asserted for channel A, negated for B)
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lrck : out std_logic := '0';
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-- Receiver has (probably) valid data on its outputs
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active: out std_logic := '0'
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);
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);
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end aes3rx;
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end aes3rx;
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|
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architecture Behavioral of aes3rx is
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architecture Behavioral of aes3rx is
|
constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111"; -- X preamble bit sequence
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-- Locking state machine states enum type
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constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111"; -- Y preamble bit sequence
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type lock_state_type is (locking, confirming, locked);
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constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111"; -- Z preamble bit sequence
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-- Constants for preamble detection
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constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111";
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signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying
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constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111";
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signal change : std_logic := '0'; -- signal signifying a change on the input
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constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111";
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signal aes3_clk : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)
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-- Input shift register for handling metastability issues and delaying input
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signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0'); -- decoder shift reg for preamble detection and logical state decoding
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signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0');
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signal align_counter : std_logic := '0'; -- 1 bit counter reset on preamble detection, provides correct bit alignement for decoder
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-- Change signal, active high on input transition
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signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration
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signal change : std_logic := '0';
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signal sync_timer : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes
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-- Recovered AES3 clock, stream of pulses
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signal reg_clk_period : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflow, serves as reference for aes3 clock regeneration
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signal aes3_clk : std_logic := '0';
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-- Shift register for preamble detection and data decoding
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signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0');
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-- 1 bit counter used for correct decoder_shift alignment for data decoder
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signal align_counter : std_logic := '0';
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-- Counter for AES3 clk regeneration
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signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0');
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-- Counts aes3_clk pulses per frame (for locking reasons)
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signal sync_cnt : std_logic_vector(5 downto 0) := (others => '0');
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-- Period register for clk_counter
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signal reg_clk_period : std_logic_vector(reg_width - 1 downto 0) := (others => '1');
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-- Asserted when locking state machine is not in locked state
|
signal sync_lost : std_logic := '1';
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signal sync_lost : std_logic := '1';
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-- Asserted when preamble has been detected
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signal preamble_detected: std_logic := '0';
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signal preamble_detected: std_logic := '0';
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-- Internal version of bsync signal
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signal sdata_int : std_logic := '0'; -- internal sdata signal
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signal bsync_int : std_logic := '0';
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signal bsync_int : std_logic := '0'; -- internal bsync signal
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-- Internal version of lrck signal
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signal lrck_int : std_logic := '0'; -- internal lrck signal
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signal lrck_int : std_logic := '0';
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-- Internal version of sdata signal
|
signal clk : std_logic := '0';
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signal sdata_int : std_logic := '0';
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-- State of locking state machine
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signal lock_state : lock_state_type := locking;
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-- Next state of locking state machine
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signal lock_state_next : lock_state_type;
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-- Signal indicating some error in received AES3, used primarily by locking state machine
|
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signal lock_error : std_logic;
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-- Asserted when sync_cnt is full (i.e. it has value of 63)
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|
signal sync_cnt_full : std_logic;
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-- Asserted when there was at least one aes3_clk pulse since last input transition
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signal aes3_clk_activity: std_logic := '0';
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-- Signals indicating detection of X, Y and Z preambles
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signal x_detected : std_logic := '0';
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signal y_detected : std_logic := '0';
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signal z_detected : std_logic := '0';
|
begin
|
begin
|
|
|
clk <= clk_in;
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-- Carries out input double sampling in order to avoid metastable states on FFs and creation
|
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-- of delayed signals for change detector (1 clk period) and decoder (2 clk periods).
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------------------------------------------
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-- input_shift_reg_proc
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-- Carries out input double sampling in
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-- order to avoid metastable states on FFs
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-- and creation of delayed signals for
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-- change detector (1 clk period) and
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-- decoder (2 clk periods)
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------------------------------------------
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input_shift_reg_proc: process (clk)
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input_shift_reg_proc: process (clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
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if reset = '1' then
|
if reset = '1' then
|
aes3_sync <= (others => '0');
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aes3_sync <= (others => '0');
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| Line 77... |
Line 96... |
aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg
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aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg
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end if;
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end if;
|
end if;
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end if;
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end process;
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end process;
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|
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------------------------------------------
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-- Detects edge on sampled input in the way of comparsion of delayed input and its current
|
-- change_detect_proc
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-- state on XOR gate.
|
-- Detects edge on sampled input in the
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-- way of comparsion of delayed input
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-- and current state on XOR gate
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|
------------------------------------------
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change_detect_proc: process (clk)
|
change_detect_proc: process (clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if reset = '1' then
|
if reset = '1' then
|
change <= '0';
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change <= '0';
|
else
|
else
|
change <= '0';
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change <= aes3_sync(2) xor aes3_sync(1);
|
if aes3_sync(2) /= aes3_sync(1) then
|
end if;
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change <= '1';
|
|
end if;
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end if;
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end process;
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-- Counts number of aes3_clk pulses since last preamble detection, used by locking state machine
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sync_cnt_proc: process (clk)
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|
begin
|
|
if clk'event and clk ='1' then
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if reset = '1' then
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sync_cnt <= (others => '0');
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elsif aes3_clk = '1' then
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if preamble_detected = '1' then
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sync_cnt <= (others => '0');
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else
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sync_cnt <= sync_cnt + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Comparator driving sync_cnt_full signal
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sync_cnt_comp: process(sync_cnt)
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begin
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if sync_cnt = 63 then
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sync_cnt_full <= '1';
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else
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sync_cnt_full <= '0';
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end if;
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end process;
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end process;
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aes3_clk_feedback: process (clk)
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-- Lock error occurs when sync_cnt is full and no preamble has been detected (i.e. when the
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-- aes3_clk pulse generation speed is too high) or preamble is detected and sync_cnt is not full
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-- (when aes3_clk pulse rate is too low) or when since last input transition there was no
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-- aes3_clk pulse at all (value of reg_clk_period is a way too high)
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lock_error <= (sync_cnt_full and not preamble_detected) or
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(not sync_cnt_full and preamble_detected) or
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(change and not aes3_clk_activity);
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-- Counter holding aes3_clk period duration. The receiver tries to receive a valid frame using
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-- counter's (which is initially all ones) output, if it fails, counter is enabled to lower its
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-- value by one (counter is also enabled when aes3_clk_activity is low on input transition -
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-- which indicates that value of reg_clk_period is way too high and no aes3_clk pulses are being
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-- generated) and this new value is tried. This process is repeated until lock is not acquired.
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-- This solution consumes less logic than direct measurement of shortest AES3 symbol and is actually
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-- more reliable. Lock time is fast enough (will always be under 2**(reg_width + 1) frames, but very
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-- likely much faster thanks to initial rapid speed of counting which is given by no activity on
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-- aes3_clk signal).
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aes3_clk_period_proc: process(clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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reg_clk_period <= (others => '1');
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reg_clk_period <= (others => '1');
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sync_timer <= (others => '0');
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elsif (lock_state = locked and lock_state_next = locking) then
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else
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reg_clk_period <= (others => '1');
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elsif (aes3_clk = '1' and sync_cnt_full = '1' and lock_state_next = locking) or
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(change = '1' and aes3_clk_activity = '0') then
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reg_clk_period <= reg_clk_period - 1;
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end if;
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end if;
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end process;
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-- Locking state machine. While initialized in locking state, waits for preamble_detection - once one
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-- has been detected, state machine is transitioned to confirming state. When no locking error
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-- occurs during one next frame, receiver is considered locked and state accordingly changes. Otherwise
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-- the state machine falls back to locking state.
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lock_state_machine: process (lock_state, preamble_detected, sync_cnt_full,
|
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lock_error)
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begin
|
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case lock_state is
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when locking =>
|
if preamble_detected = '1' then
|
if preamble_detected = '1' then
|
sync_timer <= (others => '0');
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lock_state_next <= confirming;
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else
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lock_state_next <= locking;
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end if;
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when confirming =>
|
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if lock_error = '1' then
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lock_state_next <= locking;
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elsif sync_cnt_full = '1' and preamble_detected = '1' then
|
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lock_state_next <= locked;
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else
|
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lock_state_next <= confirming;
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|
end if;
|
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when locked =>
|
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if lock_error = '1' then
|
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lock_state_next <= locking;
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else
|
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lock_state_next <= locked;
|
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end if;
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end case;
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end process;
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|
|
-- When state of locking state machine is other than locked, sync_lost signal is asserted.
|
|
sync_lost_proc: process (lock_state)
|
|
begin
|
|
if lock_state = locked then
|
sync_lost <= '0';
|
sync_lost <= '0';
|
elsif aes3_clk = '1' then
|
|
if sync_timer = 63 then
|
|
if sync_lost = '1' then
|
|
reg_clk_period <= reg_clk_period - 1;
|
|
else
|
else
|
reg_clk_period <= (others => '1');
|
|
sync_lost <= '1';
|
sync_lost <= '1';
|
end if;
|
end if;
|
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end process;
|
|
|
|
-- Synchronization process for locking state machine
|
|
lock_state_machinine_sync_proc: process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if reset = '1' then
|
|
lock_state <= locking;
|
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elsif aes3_clk = '1' or (change = '1' and aes3_clk_activity = '0') then
|
|
lock_state <= lock_state_next;
|
end if;
|
end if;
|
sync_timer <= sync_timer + 1;
|
|
end if;
|
end if;
|
|
end process;
|
|
|
|
-- Counter for aes3_clk generation. On input transition, counter is loaded with approx. half
|
|
-- of reg_clk_period, which should create 90 degrees phase shift of regenerated clock in respect
|
|
-- to delayed input and thus ensure that input will be sampled in approximate middle of 1UI symbol
|
|
-- (or in the middle of one half of 2UI symbol or in the middle of one third of 3UI symbol).
|
|
-- Otherwise, when no transition has been detected on input and clk_counter counts to zero, full
|
|
-- reg_clk_period is loaded into the counter to create aes3_clk pulses when 2UI and 3UI symbols are
|
|
-- being received.
|
|
aes3_clk_cnt_proc: process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if reset = '1' then
|
|
clk_counter <= (others => '0');
|
|
elsif change = '1' or clk_counter = 0 then
|
|
if change = '1' then
|
|
clk_counter <= '0' & reg_clk_period(reg_width - 1 downto 1);
|
|
else
|
|
clk_counter <= reg_clk_period;
|
|
end if;
|
|
else
|
|
clk_counter <= clk_counter - 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
aes3_clk_regen_proc: process (clk)
|
-- Generates aes3_clk pulse when clk_counter counts to zero.
|
|
process (clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if reset = '1' then
|
if reset = '1' then
|
clk_counter <= (others => '0');
|
|
aes3_clk <= '0';
|
aes3_clk <= '0';
|
else
|
else
|
clk_counter <= clk_counter - 1;
|
if clk_counter = 0 then
|
|
aes3_clk <= '1';
|
|
else
|
aes3_clk <= '0';
|
aes3_clk <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- Monitors activity on aes3_clk
|
|
process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if reset = '1' then
|
|
aes3_clk_activity <= '0';
|
|
else
|
if change = '1' then
|
if change = '1' then
|
clk_counter <= '0' & reg_clk_period(reg_width - 1 downto 1);
|
aes3_clk_activity <= '0';
|
elsif clk_counter = 0 then
|
elsif clk_counter = 0 then
|
clk_counter <= reg_clk_period;
|
aes3_clk_activity <= '1';
|
aes3_clk <= '1';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
------------------------------------------
|
-- Eight bit shift register for preamble detection and decoder functionality.
|
-- decoder_shift_reg_proc
|
|
-- Eight bit shift register for preamble
|
|
-- detection and decoder functionality.
|
|
------------------------------------------
|
|
decoder_shift_reg_proc: process (clk)
|
decoder_shift_reg_proc: process (clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if reset = '1' then
|
if reset = '1' then
|
decoder_shift <= (others => '0');
|
decoder_shift <= (others => '0');
|
| Line 157... |
Line 287... |
decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
|
decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
------------------------------------------
|
-- Preamble detectors (implemented using comparators)
|
-- decoder_proc
|
x_preamble_detector: process(decoder_shift)
|
-- Compares shift register with preamble
|
begin
|
-- bit sequences and when one is detected,
|
if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
|
-- accoridngly changes sync signals and
|
x_detected <= '1';
|
-- resets bit alignment counter
|
else
|
-- (align_counter). Bits are decoded when
|
x_detected <= '0';
|
-- align_counter is high.
|
end if;
|
------------------------------------------
|
end process;
|
decoder_proc: process (clk)
|
|
|
y_preamble_detector: process(decoder_shift)
|
|
begin
|
|
if decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
|
|
y_detected <= '1';
|
|
else
|
|
y_detected <= '0';
|
|
end if;
|
|
end process;
|
|
|
|
z_preamble_detector: process(decoder_shift)
|
|
begin
|
|
if decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
|
|
z_detected <= '1';
|
|
else
|
|
z_detected <= '0';
|
|
end if;
|
|
end process;
|
|
|
|
preamble_detected <= x_detected or y_detected or z_detected;
|
|
|
|
-- One bit counter used for correct bit alignment on bit decoder. Align_counter is reset on
|
|
-- preamble detection and thus allows decoder to be correctly aligned with sampled symbol beginning.
|
|
align_cnt_proc: process(clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if reset = '1' then
|
if reset = '1' then
|
lrck_int <= '0';
|
align_counter <= '0';
|
bsync_int <= '0';
|
elsif aes3_clk = '1' then
|
|
if preamble_detected = '1' then
|
align_counter <= '0';
|
align_counter <= '0';
|
else
|
else
|
if aes3_clk = '1' then
|
|
align_counter <= not align_counter;
|
align_counter <= not align_counter;
|
preamble_detected <= '0';
|
|
if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
|
|
preamble_detected <= '1';
|
|
align_counter <= '0';
|
|
bsync_int <= '0';
|
|
lrck_int <= '1';
|
|
elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
|
|
preamble_detected <= '1';
|
|
align_counter <= '0';
|
|
bsync_int <= '0';
|
|
lrck_int <= '0';
|
|
elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
|
|
preamble_detected <= '1';
|
|
align_counter <= '0';
|
|
bsync_int <= '1';
|
|
lrck_int <= '1';
|
|
end if;
|
end if;
|
if align_counter = '1' then
|
|
if decoder_shift(5) = decoder_shift(4) then
|
|
sdata_int <= '0';
|
|
else
|
|
sdata_int <= '1';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
|
|
|
-- Drives lrck and bsync signals
|
|
frame_block_sync_proc: process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if aes3_clk = '1' and preamble_detected = '1' then
|
|
lrck_int <= x_detected or z_detected;
|
|
bsync_int <= z_detected;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
|
|
|
-- Eight bit shift register for preamble detection and decoder functionality.
|
|
bbbr_shift_reg_proc: process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if reset = '1' then
|
|
decoder_shift <= (others => '0');
|
|
elsif aes3_clk = '1' then
|
|
decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
|
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
-- Two consecutive sampled symbols, when equal, are considered as logical 0. Two consecutive sampled
|
|
-- symbols, when differs, are considered as logical 1. This logical value is then shifted into
|
|
-- data_shift_reg.
|
|
data_shift_reg_proc: process (clk)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if aes3_clk = '1' and align_counter = '1' then
|
|
sdata_int <= decoder_shift(1) xor decoder_shift(0);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- Synchronization and activity signals outputs
|
activity_eval_proc: process (clk)
|
activity_eval_proc: process (clk)
|
begin
|
begin
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
active <= not sync_lost;
|
active <= not sync_lost;
|
sclk <= align_counter and not sync_lost;
|
|
sdata <= sdata_int and not sync_lost;
|
|
lrck <= lrck_int and not sync_lost;
|
lrck <= lrck_int and not sync_lost;
|
bsync <= bsync_int and not sync_lost;
|
bsync <= bsync_int and not sync_lost;
|
|
sclk <= align_counter and not sync_lost;
|
|
sdata <= sdata_int and not sync_lost;
|
end if;
|
end if;
|
end process;
|
end process;
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
No newline at end of file
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No newline at end of file
|
