----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company: Czech Television
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-- Company: Czech Television
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-- Engineer: Petr Nohavica
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-- Engineer: Petr Nohavica
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--
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--
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-- Create Date: 09:02:45 05/09/2009
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-- Create Date: 09:02:45 05/09/2009
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-- Module Name: aes3rx - Behavioral
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-- Module Name: aes3rx - Behavioral
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-- Project Name: AES3 minimalistic receiver
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-- Project Name: AES3 minimalistic receiver
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-- Target Devices: Spartan 3
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-- Target Devices: Spartan 3
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-- Tool versions: ISE 10.1
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-- Tool versions: ISE 10.1
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity aes3rx is
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entity aes3rx is
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generic (
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generic (
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reg_width : integer := 5
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reg_width : integer := 4
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);
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);
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port (
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port (
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clk : in std_logic; -- master clock
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clk_in: in std_logic; -- master clock
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aes3 : in std_logic; -- input
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aes3 : in std_logic; -- input
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reset : in std_logic; -- synchronous reset
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reset : in std_logic; -- synchronous reset
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sdata : out std_logic := '0'; -- output serial data
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sdata : out std_logic := '0'; -- output serial data
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sclk : out std_logic := '0'; -- output serial data clock
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sclk : out std_logic := '0'; -- output serial data clock
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bsync : out std_logic := '0'; -- block start (high when Z subframe is being transmitted)
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bsync : out std_logic := '0'; -- block start (high when Z subframe is being transmitted)
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fsync : out std_logic := '0'; -- frame sync (high for channel A, low for B)
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lrck : out std_logic := '0'; -- frame sync (high for channel A, low for B)
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active: out std_logic := '0' -- receiver has valid data on its outputs
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active: out std_logic := '0' -- receiver has valid data on its outputs
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);
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);
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end aes3rx;
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end aes3rx;
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architecture Behavioral of aes3rx is
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architecture Behavioral of aes3rx is
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constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111"; -- X preamble bit sequence
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constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111"; -- X preamble bit sequence
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constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111"; -- Y preamble bit sequence
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constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111"; -- Y preamble bit sequence
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constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111"; -- Z preamble bit sequence
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constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111"; -- Z preamble bit sequence
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signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying
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signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying
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signal change : std_logic := '0'; -- signal signifying a change on the input
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signal change : std_logic := '0'; -- signal signifying a change on the input
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signal aes3_clk : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)
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signal aes3_clk : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)
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signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0'); -- decoder shift reg for preamble detection and logical state decoding
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signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0'); -- decoder shift reg for preamble detection and logical state decoding
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signal align_counter : std_logic := '0'; -- 1 bit counter reset on preamble detection, provides correct bit alignement for decoder
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signal align_counter : std_logic := '0'; -- 1 bit counter reset on preamble detection, provides correct bit alignement for decoder
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signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration
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signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration
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signal dur_counter : std_logic_vector(reg_width + 1 downto 0) := (others => '0'); -- counts durration (in clk periods) of current input invariant state (i.e. from "edge to edge")
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signal sync_timer : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes
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signal upd_timer : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes
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signal reg_clk_period : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflow, serves as reference for aes3 clock regeneration
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signal reg_reset : std_logic := '0'; -- resets reg_shortest on upd_timer overflow
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signal sync_lost : std_logic := '1';
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signal reg_shortest : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- stores durration of shortest measured input invariant state
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signal preamble_detected: std_logic := '0';
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signal reg_shortest_ref : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflow, serves as reference for aes3 clock regeneration
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signal sdata_int : std_logic := '0'; -- internal sdata signal
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signal sdata_int : std_logic := '0'; -- internal sdata signal
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signal bsync_int : std_logic := '0'; -- internal bsync signal
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signal bsync_int : std_logic := '0'; -- internal bsync signal
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signal fsync_int : std_logic := '0'; -- internal fsync signal
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signal lrck_int : std_logic := '0'; -- internal lrck signal
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signal active_int : std_logic := '0'; -- internal active signal
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signal sync_ok : std_logic := '0'; -- set high on preamble detection, set low on timeout
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signal clk : std_logic := '0';
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signal timeout : std_logic := '1'; -- when input pulse is too long, set high
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begin
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begin
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clk <= clk_in;
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------------------------------------------
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------------------------------------------
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-- input_shift_reg_proc
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-- input_shift_reg_proc
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-- Carries out input double sampling in
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-- Carries out input double sampling in
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-- order to avoid metastable states on FFs
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-- order to avoid metastable states on FFs
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-- and creation of delayed signals for
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-- and creation of delayed signals for
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-- change detector (1 clk period) and
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-- change detector (1 clk period) and
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-- decoder (2 clk periods)
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-- decoder (2 clk periods)
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------------------------------------------
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------------------------------------------
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input_shift_reg_proc: process (clk)
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input_shift_reg_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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aes3_sync <= (others => '0');
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aes3_sync <= (others => '0');
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else
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else
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aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg
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aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------
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------------------------------------------
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-- change_detect_proc
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-- change_detect_proc
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-- Detects edge on sampled input in the
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-- Detects edge on sampled input in the
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-- way of comparsion of delayed input
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-- way of comparsion of delayed input
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-- and current state on XOR gate
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-- and current state on XOR gate
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------------------------------------------
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------------------------------------------
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change_detect_proc: process (clk)
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change_detect_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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change <= '0';
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change <= '0';
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else
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else
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change <= '0';
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change <= '0';
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if aes3_sync(2) /= aes3_sync(1) then
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if aes3_sync(2) /= aes3_sync(1) then
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change <= '1';
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change <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------
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aes3_clk_feedback: process (clk)
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-- shortest_pulse_dur_cnt_proc
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-- dur_counter counts number of clocks
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-- between two input transitions and thus
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-- effeciently measuring input pulse
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-- (relative) durration. When input
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-- changes its state, counter value is
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-- compared with reg_shortest and if
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-- counter's value is smaller than
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-- register's one, reg_shortest is updated
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-- from the counter.
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------------------------------------------
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shortest_pulse_dur_cnt_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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reg_shortest <= (others => '1');
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reg_clk_period <= (others => '1');
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dur_counter <= (others => '0');
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sync_timer <= (others => '0');
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else
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else
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if change = '1' then
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if preamble_detected = '1' then
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timeout <= '0';
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sync_timer <= (others => '0');
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if dur_counter < reg_shortest then
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sync_lost <= '0';
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reg_shortest <= dur_counter(reg_width - 1 downto 0);
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elsif aes3_clk = '1' then
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end if;
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if sync_timer = 63 then
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dur_counter <= (others => '0');
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if sync_lost = '1' then
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elsif dur_counter = 2**(reg_width + 2) - 1 then
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reg_clk_period <= reg_clk_period - 1;
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timeout <= '1';
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else
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else
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dur_counter <= dur_counter + 1;
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reg_clk_period <= (others => '1');
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sync_lost <= '1';
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end if;
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end if;
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if reg_reset = '1' then
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reg_shortest <= (others => '1');
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end if;
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end if;
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end if;
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sync_timer <= sync_timer + 1;
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end if;
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end process;
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------------------------------------------
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-- register_update_timer_proc
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-- upd_timer is incremented by one when
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-- change is detected on input. When 63
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-- changes count is reached, reg_shortest
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-- is copied to reg_shortest_ref and
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-- reg_reset (which resets reg_shortest
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-- in shortest_pulse_dur_cnt_proc) is
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-- raised. 63 change count guarantees that
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-- there was at least one "short" pulse
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-- on input.
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------------------------------------------
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register_update_timer_proc: process (clk)
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begin
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if clk'event and clk = '1' then
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reg_reset <= '0';
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if reset = '1' then
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reg_shortest_ref <= (others => '1');
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upd_timer <= (others => '0');
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else
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if change = '1' then
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if upd_timer = 63 then
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reg_shortest_ref <= reg_shortest;
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reg_reset <= '1';
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end if;
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upd_timer <= upd_timer + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------
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-- aes3_clk_regen_proc
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-- Process regenerating clock from input.
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-- When clk_counter counts to zero, pulse
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-- one master clock period wide is created
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-- on aes3_clk and counter is loaded with
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-- reg_shortest_ref, which stores
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-- supposed input clock half period
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-- (relatively to master clock, indeed).
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-- When change on input is detected,
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-- clk_counter is loaded with approx. half
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-- of reg_shortest_reg, thus ensuring that
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-- next pulse will be generated in the
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-- middle of input invariant state and
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-- aes3_clk is effectively resynchronized
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-- with input. aes3_clk is then
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-- delayed by approx. one half of shortest
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-- input pulse with respect to input
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-- changes to provide decoder ideal
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-- sampling moments and to ensure that,
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-- when there are no transitions on input
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-- (and aes3_clk is in "free run"),
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-- there will be accurate clock pulse
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-- count generated.
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------------------------------------------
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aes3_clk_regen_proc: process (clk)
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aes3_clk_regen_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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clk_counter <= (others => '0');
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clk_counter <= (others => '0');
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aes3_clk <= '0';
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aes3_clk <= '0';
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else
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else
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clk_counter <= clk_counter - 1;
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clk_counter <= clk_counter - 1;
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aes3_clk <= '0';
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aes3_clk <= '0';
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if change = '1' then
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if change = '1' then
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clk_counter <= '0' & reg_shortest_ref(reg_width - 1 downto 1);
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clk_counter <= '0' & reg_clk_period(reg_width - 1 downto 1);
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elsif clk_counter = 0 then
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elsif clk_counter = 0 then
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clk_counter <= reg_shortest_ref;
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clk_counter <= reg_clk_period;
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aes3_clk <= '1';
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aes3_clk <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------
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------------------------------------------
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-- decoder_shift_reg_proc
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-- decoder_shift_reg_proc
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-- Eight bit shift register for preamble
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-- Eight bit shift register for preamble
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-- detection and decoder functionality.
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-- detection and decoder functionality.
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------------------------------------------
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------------------------------------------
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decoder_shift_reg_proc: process (clk)
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decoder_shift_reg_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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decoder_shift <= (others => '0');
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decoder_shift <= (others => '0');
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elsif aes3_clk = '1' then
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elsif aes3_clk = '1' then
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decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
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decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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------------------------------------------
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------------------------------------------
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-- decoder_proc
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-- decoder_proc
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-- Compares shift register with preamble
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-- Compares shift register with preamble
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-- bit sequences and when one is detected,
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-- bit sequences and when one is detected,
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-- accoridngly changes sync signals and
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-- accoridngly changes sync signals and
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-- resets bit alignment counter
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-- resets bit alignment counter
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-- (align_counter). Data is decoded when
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-- (align_counter). Bits are decoded when
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-- align_counter is high.
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-- align_counter is high.
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------------------------------------------
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------------------------------------------
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decoder_proc: process (clk)
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decoder_proc: process (clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if reset = '1' then
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if reset = '1' then
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fsync_int <= '0';
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lrck_int <= '0';
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bsync_int <= '0';
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bsync_int <= '0';
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sync_ok <= '0';
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align_counter <= '0';
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align_counter <= '0';
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else
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else
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if timeout = '1' then
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sync_ok <= '0';
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end if;
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if aes3_clk = '1' then
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if aes3_clk = '1' then
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align_counter <= not align_counter;
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align_counter <= not align_counter;
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preamble_detected <= '0';
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if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
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if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
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fsync_int <= '1';
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preamble_detected <= '1';
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bsync_int <= '0';
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sync_ok <= '1';
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align_counter <= '0';
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align_counter <= '0';
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elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
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fsync_int <= '0';
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bsync_int <= '0';
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bsync_int <= '0';
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sync_ok <= '1';
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lrck_int <= '1';
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elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
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preamble_detected <= '1';
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align_counter <= '0';
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align_counter <= '0';
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bsync_int <= '0';
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lrck_int <= '0';
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elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
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elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
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fsync_int <= '1';
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preamble_detected <= '1';
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bsync_int <= '1';
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sync_ok <= '1';
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align_counter <= '0';
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align_counter <= '0';
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bsync_int <= '1';
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lrck_int <= '1';
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end if;
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end if;
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if align_counter = '1' then
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if align_counter = '1' then
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if decoder_shift(1) = decoder_shift(0) then
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if decoder_shift(5) = decoder_shift(4) then
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sdata_int <= '0';
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sdata_int <= '0';
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else
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else
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sdata_int <= '1';
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sdata_int <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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active_int <= sync_ok and not timeout and not reset;
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activity_eval_proc: process (clk)
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sclk <= align_counter and active_int;
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begin
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sdata <= sdata_int and active_int;
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if clk'event and clk = '1' then
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fsync <= fsync_int and active_int;
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active <= not sync_lost;
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bsync <= bsync_int and active_int;
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sclk <= align_counter and not sync_lost;
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active <= active_int;
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sdata <= sdata_int and not sync_lost;
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lrck <= lrck_int and not sync_lost;
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bsync <= bsync_int and not sync_lost;
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end if;
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end process;
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end Behavioral;
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end Behavioral;
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