| Line 1... |
Line 1... |
|
//---------------------------------------------------------------------------------------
|
|
// Project: High Throughput & Low Area AES Core
|
|
//
|
|
// File name: tb_kat.v (Jan 1, 2011)
|
|
//
|
|
// Writer: Moti Litochevski
|
|
//
|
|
// Description:
|
|
// This file contains the core test bench to check compatibility with the Known
|
|
// Answer Test (KAT) vectors. The test bench runs all files listed in the
|
|
// "KAT_files.txt" file.
|
|
// Note that only ECB mode test vectors should be included since other modes require
|
|
// additional logic to be implemented around the AES algorithm core.
|
|
//
|
|
// Revision History:
|
|
//
|
|
// Rev <revnumber> <Date> <owner>
|
|
// <comment>
|
|
//
|
|
//---------------------------------------------------------------------------------------
|
|
|
`timescale 1ns / 10ps
|
`timescale 1ns / 10ps
|
|
|
module test ();
|
module test ();
|
|
|
// define input list file name
|
// define input list file name
|
`define IN_FILE "KAT_files.txt"
|
`define IN_FILE "KAT_files.txt"
|
|
|
| Line 16... |
Line 38... |
`define CHAR_Z 8'h5A
|
`define CHAR_Z 8'h5A
|
`define CHAR_a 8'h61
|
`define CHAR_a 8'h61
|
`define CHAR_f 8'h66
|
`define CHAR_f 8'h66
|
`define CHAR_z 8'h7A
|
`define CHAR_z 8'h7A
|
|
|
|
//---------------------------------------------------------------------------------------
|
// test bench signals
|
// test bench signals
|
reg clk;
|
reg clk;
|
reg reset;
|
reg reset;
|
reg [255:0] in_file_name;
|
reg [255:0] in_file_name;
|
reg key_start, enc_dec, data_in_valid, enable, test_start;
|
reg key_start, enc_dec, data_in_valid, enable, test_start;
|
| Line 117... |
Line 140... |
// return the resulting value
|
// return the resulting value
|
char2val = out_val;
|
char2val = out_val;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
//---------------------------------------------------------------------------------------
|
|
// test bench implementation
|
// global clock generator
|
// global clock generator
|
initial clk = 1'b1;
|
initial clk = 1'b1;
|
always #10 clk = ~clk;
|
always #10 clk = ~clk;
|
|
|
// gloabl reset generator
|
// gloabl reset generator
|
| Line 449... |
Line 474... |
always @ (posedge clk)
|
always @ (posedge clk)
|
if (data_out_valid)
|
if (data_out_valid)
|
$display("Data Out: %16h",data_out);
|
$display("Data Out: %16h",data_out);
|
|
|
endmodule
|
endmodule
|
|
//---------------------------------------------------------------------------------------
|
|
// Th.. Th.. Th.. Thats all folks !!!
|
|
//---------------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
