| Line 12... |
Line 12... |
//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module key_exp (
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module key_exp (
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clk,
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clk,
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reset_n,
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reset,
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key_in,
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key_in,
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key_mode,
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key_mode,
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key_start,
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key_start,
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wr,
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wr,
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wr_addr,
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wr_addr,
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wr_data,
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wr_data,
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key_ready
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key_ready
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);
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);
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|
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input clk;
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input clk;
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input reset_n;
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input reset;
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input [255:0] key_in; // initial key value
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input [255:0] key_in; // initial key value
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input [1:0] key_mode; // 0:128, 1:192, 2:256
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input [1:0] key_mode; // 0:128, 1:192, 2:256
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input key_start;// start key expansion
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input key_start;// start key expansion
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output wr; // key expansion ram interface
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output wr; // key expansion ram interface
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output [4:0] wr_addr;
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output [4:0] wr_addr;
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| Line 62... |
Line 62... |
GENKEY_256 = 2'b11;
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GENKEY_256 = 2'b11;
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|
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assign max_round_p1[3:0] = (key_mode == 2'b00) ? 4'd11 : (key_mode == 2'b01 ? 4'd13 : 4'd15);
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assign max_round_p1[3:0] = (key_mode == 2'b00) ? 4'd11 : (key_mode == 2'b01 ? 4'd13 : 4'd15);
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// rcon generation
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// rcon generation
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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rcon[31:0] <= 32'h01000000;
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rcon[31:0] <= 32'h01000000;
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rcon_is_1b <= 1'b0;
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rcon_is_1b <= 1'b0;
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end
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end
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else if (key_start)
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else if (key_start)
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| Line 95... |
Line 95... |
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/*****************************************************************************/
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/*****************************************************************************/
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// State machine for Key expansion
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// State machine for Key expansion
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//
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//
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//
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//
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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state[1:0] <= IDLE;
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state[1:0] <= IDLE;
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pstate[1:0] <= IDLE;
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pstate[1:0] <= IDLE;
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end
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end
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else
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else
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| Line 144... |
Line 144... |
end
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end
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endcase
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endcase
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end
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end
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// round counter: 10/12/14
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// round counter: 10/12/14
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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round[3:0] <= 1'b0;
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round[3:0] <= 1'b0;
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else if (nstate[1:0] == IDLE)
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else if (nstate[1:0] == IDLE)
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round[3:0] <= 4'b0;
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round[3:0] <= 4'b0;
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else if (state[1:0] == START)
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else if (state[1:0] == START)
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round[3:0] <= round[3:0] + 1'b1;
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round[3:0] <= round[3:0] + 1'b1;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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sbox_in_valid <= 1'b0;
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sbox_in_valid <= 1'b0;
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sbox_in[31:0] <= 32'b0;
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sbox_in[31:0] <= 32'b0;
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end
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end
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else if (state[1:0] == START) // rotword
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else if (state[1:0] == START) // rotword
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| Line 180... |
Line 180... |
end
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end
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else
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else
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sbox_in_valid <= 1'b0;
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sbox_in_valid <= 1'b0;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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valid[4:0] <= 5'b0;
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valid[4:0] <= 5'b0;
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else
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else
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valid[4:0] <= {valid[3:0],sbox_in_valid};
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valid[4:0] <= {valid[3:0],sbox_in_valid};
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end
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end
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assign sbox_out_valid = valid[1];
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assign sbox_out_valid = valid[1];
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|
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sbox u_0(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[7:0]),.ende(1'b0),.en_dout(sbox_out[7:0]),.de_dout());
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sbox u_0(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[7:0]),.ende(1'b0),.en_dout(sbox_out[7:0]),.de_dout());
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sbox u_1(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[15:8]),.ende(1'b0),.en_dout(sbox_out[15:8]),.de_dout());
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sbox u_1(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[15:8]),.ende(1'b0),.en_dout(sbox_out[15:8]),.de_dout());
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sbox u_2(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[23:16]),.ende(1'b0),.en_dout(sbox_out[23:16]),.de_dout());
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sbox u_2(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[23:16]),.ende(1'b0),.en_dout(sbox_out[23:16]),.de_dout());
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sbox u_3(.clk(clk),.reset_n(reset_n),.enable(1'b1),.din(sbox_in[31:24]),.ende(1'b0),.en_dout(sbox_out[31:24]),.de_dout());
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sbox u_3(.clk(clk),.reset(reset),.enable(1'b1),.din(sbox_in[31:24]),.ende(1'b0),.en_dout(sbox_out[31:24]),.de_dout());
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|
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/*****************************************************************************/
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/*****************************************************************************/
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// key expansion calculation
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// key expansion calculation
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//
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//
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//
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//
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| Line 209... |
Line 209... |
assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0];
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assign w4_next2[31:0] = sbox_out[31:0] ^ w4[31:0];
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assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0];
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assign w5_next2[31:0] = w4_next2[31:0]^w5[31:0];
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assign w6_next[31:0] = w5_next2[31:0]^w6[31:0];
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assign w6_next[31:0] = w5_next2[31:0]^w6[31:0];
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assign w7_next[31:0] = w6_next[31:0]^w7[31:0];
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assign w7_next[31:0] = w6_next[31:0]^w7[31:0];
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= 256'b0;
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{w0[31:0],w1[31:0],w2[31:0],w3[31:0],w4[31:0],w5[31:0],w6[31:0],w7[31:0]} <= 256'b0;
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end
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end
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else if (key_start)
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else if (key_start)
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begin
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begin
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| Line 263... |
Line 263... |
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assign wr_data1[63:0] = wr_256 ?{w4[31:0],w5[31:0]} : {w0[31:0],w1[31:0]};
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assign wr_data1[63:0] = wr_256 ?{w4[31:0],w5[31:0]} : {w0[31:0],w1[31:0]};
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assign wr_data2[63:0] = wr_256 ?{w6[31:0],w7[31:0]} : {w2[31:0],w3[31:0]};
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assign wr_data2[63:0] = wr_256 ?{w6[31:0],w7[31:0]} : {w2[31:0],w3[31:0]};
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assign wr_data3[63:0] = {w4[31:0],w5[31:0]};
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assign wr_data3[63:0] = {w4[31:0],w5[31:0]};
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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else if (key_start)
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else if (key_start)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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else if (sbox_out_valid && (state[1:0] == GENKEY_256))
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else if (sbox_out_valid && (state[1:0] == GENKEY_256))
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wr_256 <= 1'b1;
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wr_256 <= 1'b1;
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else if (sbox_out_valid)
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else if (sbox_out_valid)
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wr_256 <= 1'b0;
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wr_256 <= 1'b0;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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{key_start_L3,key_start_L2,key_start_L} <= 3'b0;
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{key_start_L3,key_start_L2,key_start_L} <= 3'b0;
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else
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else
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{key_start_L3,key_start_L2,key_start_L} <= {key_start_L2,key_start_L,key_start};
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{key_start_L3,key_start_L2,key_start_L} <= {key_start_L2,key_start_L,key_start};
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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wr <= 1'b0;
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wr <= 1'b0;
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else
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else
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wr <= wr1 || wr2 || wr3 || init_wr1 || init_wr2 || init_wr3 || init_wr4;
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wr <= wr1 || wr2 || wr3 || init_wr1 || init_wr2 || init_wr3 || init_wr4;
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (!reset_n)
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if (reset)
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begin
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begin
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wr_data[63:0] <= 64'b0;
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wr_data[63:0] <= 64'b0;
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end
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end
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else
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else
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begin
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begin
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| Line 316... |
Line 316... |
else if (wr3)
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else if (wr3)
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wr_data[63:0] <= wr_data3[63:0];
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wr_data[63:0] <= wr_data3[63:0];
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end
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end
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end
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end
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
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begin
|
if (!reset_n)
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if (reset)
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wr_addr[4:0] <= 5'b0;
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wr_addr[4:0] <= 5'b0;
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else if (key_start)
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else if (key_start)
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wr_addr[4:0] <= 5'd0;
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wr_addr[4:0] <= 5'd0;
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else if (wr)
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else if (wr)
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wr_addr[4:0] <= wr_addr[4:0] + 1'b1;
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wr_addr[4:0] <= wr_addr[4:0] + 1'b1;
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end
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end
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|
|
always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or posedge reset)
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begin
|
begin
|
if (!reset_n)
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if (reset)
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key_ready <= 1'b0;
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key_ready <= 1'b0;
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else if (key_start)
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else if (key_start)
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key_ready <= 1'b0;
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key_ready <= 1'b0;
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else if (wr_addr[4:1] == max_round_p1[3:0])
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else if (wr_addr[4:1] == max_round_p1[3:0])
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key_ready <= 1'b1;
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key_ready <= 1'b1;
|
