//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// AltOR32
|
// AltOR32
|
// Alternative Lightweight OpenRisc
|
// Alternative Lightweight OpenRisc
|
// V2.1
|
// V2.1
|
// Ultra-Embedded.com
|
// Ultra-Embedded.com
|
// Copyright 2011 - 2014
|
// Copyright 2011 - 2014
|
//
|
//
|
// Email: admin@ultra-embedded.com
|
// Email: admin@ultra-embedded.com
|
//
|
//
|
// License: LGPL
|
// License: LGPL
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//
|
//
|
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
|
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
|
//
|
//
|
// This source file is free software; you can redistribute it
|
// This source file is free software; you can redistribute it
|
// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
// Public License as published by the Free Software Foundation;
|
// Public License as published by the Free Software Foundation;
|
// either version 2.1 of the License, or (at your option) any
|
// either version 2.1 of the License, or (at your option) any
|
// later version.
|
// later version.
|
//
|
//
|
// This source is distributed in the hope that it will be
|
// This source is distributed in the hope that it will be
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// details.
|
// details.
|
//
|
//
|
// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, write to the
|
// Public License along with this source; if not, write to the
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Boston, MA 02111-1307 USA
|
// Boston, MA 02111-1307 USA
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Includes
|
// Includes
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`include "altor32_defs.v"
|
`include "altor32_defs.v"
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
|
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
module cpu
|
module cpu
|
(
|
(
|
// General
|
// General
|
input clk_i /*verilator public*/,
|
input clk_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
|
|
input intr_i /*verilator public*/,
|
input intr_i /*verilator public*/,
|
input nmi_i /*verilator public*/,
|
input nmi_i /*verilator public*/,
|
output fault_o /*verilator public*/,
|
output fault_o /*verilator public*/,
|
output break_o /*verilator public*/,
|
output break_o /*verilator public*/,
|
|
|
// Instruction memory
|
// Instruction memory
|
output [31:0] imem_addr_o /*verilator public*/,
|
output [31:0] imem_addr_o /*verilator public*/,
|
input [31:0] imem_dat_i /*verilator public*/,
|
input [31:0] imem_dat_i /*verilator public*/,
|
output [2:0] imem_cti_o /*verilator public*/,
|
output [2:0] imem_cti_o /*verilator public*/,
|
output imem_cyc_o /*verilator public*/,
|
output imem_cyc_o /*verilator public*/,
|
output imem_stb_o /*verilator public*/,
|
output imem_stb_o /*verilator public*/,
|
input imem_stall_i/*verilator public*/,
|
input imem_stall_i/*verilator public*/,
|
input imem_ack_i/*verilator public*/,
|
input imem_ack_i/*verilator public*/,
|
|
|
// Data memory
|
// Data memory
|
output [31:0] dmem_addr_o /*verilator public*/,
|
output [31:0] dmem_addr_o /*verilator public*/,
|
output [31:0] dmem_dat_o /*verilator public*/,
|
output [31:0] dmem_dat_o /*verilator public*/,
|
input [31:0] dmem_dat_i /*verilator public*/,
|
input [31:0] dmem_dat_i /*verilator public*/,
|
output [3:0] dmem_sel_o /*verilator public*/,
|
output [3:0] dmem_sel_o /*verilator public*/,
|
output [2:0] dmem_cti_o /*verilator public*/,
|
output [2:0] dmem_cti_o /*verilator public*/,
|
output dmem_cyc_o /*verilator public*/,
|
output dmem_cyc_o /*verilator public*/,
|
output dmem_we_o /*verilator public*/,
|
output dmem_we_o /*verilator public*/,
|
output dmem_stb_o /*verilator public*/,
|
output dmem_stb_o /*verilator public*/,
|
input dmem_stall_i/*verilator public*/,
|
input dmem_stall_i/*verilator public*/,
|
input dmem_ack_i/*verilator public*/
|
input dmem_ack_i/*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
// Params
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
parameter BOOT_VECTOR = 32'h00000000;
|
parameter BOOT_VECTOR = 32'h00000000;
|
parameter ISR_VECTOR = 32'h00000000;
|
parameter ISR_VECTOR = 32'h00000000;
|
parameter REGISTER_FILE_TYPE = "SIMULATION";
|
parameter REGISTER_FILE_TYPE = "SIMULATION";
|
parameter ENABLE_ICACHE = "ENABLED";
|
parameter ENABLE_ICACHE = "ENABLED";
|
parameter ENABLE_DCACHE = "DISABLED";
|
parameter ENABLE_DCACHE = "DISABLED";
|
parameter SUPPORT_32REGS = "ENABLED";
|
parameter SUPPORT_32REGS = "ENABLED";
|
parameter PIPELINED_FETCH = "ENABLED";
|
parameter PIPELINED_FETCH = "ENABLED";
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Registers / Wires
|
// Registers / Wires
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// Instruction fetch
|
// Instruction fetch
|
wire fetch_rd_w;
|
wire fetch_rd_w;
|
wire [31:0] fetch_pc_w;
|
wire [31:0] fetch_pc_w;
|
wire [31:0] fetch_opcode_w;
|
wire [31:0] fetch_opcode_w;
|
wire fetch_valid_w;
|
wire fetch_valid_w;
|
|
|
// Decode opcode / PC / state
|
// Decode opcode / PC / state
|
wire [31:0] dec_opcode_w;
|
wire [31:0] dec_opcode_w;
|
wire [31:0] dec_opcode_pc_w;
|
wire [31:0] dec_opcode_pc_w;
|
wire dec_opcode_valid_w;
|
wire dec_opcode_valid_w;
|
|
|
// Register number (rA)
|
// Register number (rA)
|
wire [4:0] dec_ra_w;
|
wire [4:0] dec_ra_w;
|
|
|
// Register number (rB)
|
// Register number (rB)
|
wire [4:0] dec_rb_w;
|
wire [4:0] dec_rb_w;
|
|
|
// Destination register number (pre execute stage)
|
// Destination register number (pre execute stage)
|
wire [4:0] dec_rd_w;
|
wire [4:0] dec_rd_w;
|
|
|
// Register value (rA)
|
// Register value (rA)
|
wire [31:0] dec_ra_val_w;
|
wire [31:0] dec_ra_val_w;
|
|
|
// Register value (rB)
|
// Register value (rB)
|
wire [31:0] dec_rb_val_w;
|
wire [31:0] dec_rb_val_w;
|
|
|
// Destination register number (post execute stage)
|
// Destination register number (post execute stage)
|
wire [4:0] ex_rd_w;
|
wire [4:0] ex_rd_w;
|
|
|
// Current executing instruction
|
// Current executing instruction
|
wire [31:0] ex_opcode_w;
|
wire [31:0] ex_opcode_w;
|
|
|
// Result from execute
|
// Result from execute
|
wire [31:0] ex_result_w;
|
wire [31:0] ex_result_w;
|
wire [63:0] ex_mult_res_w;
|
wire [63:0] ex_mult_res_w;
|
|
|
// Branch request
|
// Branch request
|
wire ex_branch_w;
|
wire ex_branch_w;
|
wire [31:0] ex_branch_pc_w;
|
wire [31:0] ex_branch_pc_w;
|
wire ex_stall_w;
|
wire ex_stall_w;
|
|
|
// Register writeback value
|
// Register writeback value
|
wire [4:0] wb_rd_w;
|
wire [4:0] wb_rd_w;
|
wire [31:0] wb_rd_val_w;
|
wire [31:0] wb_rd_val_w;
|
|
|
// Register writeback enable
|
// Register writeback enable
|
wire wb_rd_write_w;
|
wire wb_rd_write_w;
|
|
|
wire [31:0] dcache_addr_w;
|
wire [31:0] dcache_addr_w;
|
wire [31:0] dcache_data_out_w;
|
wire [31:0] dcache_data_out_w;
|
wire [31:0] dcache_data_in_w;
|
wire [31:0] dcache_data_in_w;
|
wire [3:0] dcache_sel_w;
|
wire [3:0] dcache_sel_w;
|
wire dcache_we_w;
|
wire dcache_we_w;
|
wire dcache_stb_w;
|
wire dcache_stb_w;
|
wire dcache_cyc_w;
|
wire dcache_cyc_w;
|
wire dcache_ack_w;
|
wire dcache_ack_w;
|
wire dcache_stall_w;
|
wire dcache_stall_w;
|
|
|
wire icache_flush_w;
|
wire icache_flush_w;
|
wire dcache_flush_w;
|
wire dcache_flush_w;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Instruction Cache
|
// Instruction Cache
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
generate
|
generate
|
if (ENABLE_ICACHE == "ENABLED")
|
if (ENABLE_ICACHE == "ENABLED")
|
begin : ICACHE
|
begin : ICACHE
|
// Instruction cache
|
// Instruction cache
|
altor32_icache
|
altor32_icache
|
#(
|
#(
|
.BOOT_VECTOR(BOOT_VECTOR)
|
.BOOT_VECTOR(BOOT_VECTOR)
|
)
|
)
|
u_icache
|
u_icache
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
// Processor interface
|
// Processor interface
|
.rd_i(fetch_rd_w),
|
.rd_i(fetch_rd_w),
|
.pc_i(fetch_pc_w),
|
.pc_i(fetch_pc_w),
|
.instruction_o(fetch_opcode_w),
|
.instruction_o(fetch_opcode_w),
|
.valid_o(fetch_valid_w),
|
.valid_o(fetch_valid_w),
|
.invalidate_i(icache_flush_w),
|
.invalidate_i(icache_flush_w),
|
|
|
// Instruction memory
|
// Instruction memory
|
.wbm_addr_o(imem_addr_o),
|
.wbm_addr_o(imem_addr_o),
|
.wbm_dat_i(imem_dat_i),
|
.wbm_dat_i(imem_dat_i),
|
.wbm_cti_o(imem_cti_o),
|
.wbm_cti_o(imem_cti_o),
|
.wbm_cyc_o(imem_cyc_o),
|
.wbm_cyc_o(imem_cyc_o),
|
.wbm_stb_o(imem_stb_o),
|
.wbm_stb_o(imem_stb_o),
|
.wbm_stall_i(imem_stall_i),
|
.wbm_stall_i(imem_stall_i),
|
.wbm_ack_i(imem_ack_i)
|
.wbm_ack_i(imem_ack_i)
|
);
|
);
|
end
|
end
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// No instruction cache
|
// No instruction cache
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else
|
else
|
begin : NO_ICACHE
|
begin : NO_ICACHE
|
altor32_noicache
|
altor32_noicache
|
u_icache
|
u_icache
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
// Processor interface
|
// Processor interface
|
.rd_i(fetch_rd_w),
|
.rd_i(fetch_rd_w),
|
.pc_i(fetch_pc_w),
|
.pc_i(fetch_pc_w),
|
.instruction_o(fetch_opcode_w),
|
.instruction_o(fetch_opcode_w),
|
.valid_o(fetch_valid_w),
|
.valid_o(fetch_valid_w),
|
.invalidate_i(icache_flush_w),
|
.invalidate_i(icache_flush_w),
|
|
|
// Instruction memory
|
// Instruction memory
|
.wbm_addr_o(imem_addr_o),
|
.wbm_addr_o(imem_addr_o),
|
.wbm_dat_i(imem_dat_i),
|
.wbm_dat_i(imem_dat_i),
|
.wbm_cti_o(imem_cti_o),
|
.wbm_cti_o(imem_cti_o),
|
.wbm_cyc_o(imem_cyc_o),
|
.wbm_cyc_o(imem_cyc_o),
|
.wbm_stb_o(imem_stb_o),
|
.wbm_stb_o(imem_stb_o),
|
.wbm_stall_i(imem_stall_i),
|
.wbm_stall_i(imem_stall_i),
|
.wbm_ack_i(imem_ack_i)
|
.wbm_ack_i(imem_ack_i)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Instruction Fetch
|
// Instruction Fetch
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
altor32_fetch
|
altor32_fetch
|
#(
|
#(
|
.BOOT_VECTOR(BOOT_VECTOR),
|
.BOOT_VECTOR(BOOT_VECTOR),
|
.PIPELINED_FETCH(PIPELINED_FETCH)
|
.PIPELINED_FETCH(PIPELINED_FETCH)
|
)
|
)
|
u_fetch
|
u_fetch
|
(
|
(
|
// General
|
// General
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
// Instruction memory
|
// Instruction memory
|
.pc_o(fetch_pc_w),
|
.pc_o(fetch_pc_w),
|
.data_i(fetch_opcode_w),
|
.data_i(fetch_opcode_w),
|
.fetch_o(fetch_rd_w),
|
.fetch_o(fetch_rd_w),
|
.data_valid_i(fetch_valid_w),
|
.data_valid_i(fetch_valid_w),
|
|
|
// Fetched opcode
|
// Fetched opcode
|
.opcode_o(dec_opcode_w),
|
.opcode_o(dec_opcode_w),
|
.opcode_pc_o(dec_opcode_pc_w),
|
.opcode_pc_o(dec_opcode_pc_w),
|
.opcode_valid_o(dec_opcode_valid_w),
|
.opcode_valid_o(dec_opcode_valid_w),
|
|
|
// Branch target
|
// Branch target
|
.branch_i(ex_branch_w),
|
.branch_i(ex_branch_w),
|
.branch_pc_i(ex_branch_pc_w),
|
.branch_pc_i(ex_branch_pc_w),
|
.stall_i(ex_stall_w),
|
.stall_i(ex_stall_w),
|
|
|
// Decoded register details
|
// Decoded register details
|
.ra_o(dec_ra_w),
|
.ra_o(dec_ra_w),
|
.rb_o(dec_rb_w),
|
.rb_o(dec_rb_w),
|
.rd_o(dec_rd_w)
|
.rd_o(dec_rd_w)
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// [Xilinx] Register file
|
// [Xilinx] Register file
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
generate
|
generate
|
if (REGISTER_FILE_TYPE == "XILINX")
|
if (REGISTER_FILE_TYPE == "XILINX")
|
begin : REGFILE_XIL
|
begin : REGFILE_XIL
|
altor32_regfile_xil
|
altor32_regfile_xil
|
#(
|
#(
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
)
|
)
|
u_regfile
|
u_regfile
|
(
|
(
|
// Clocking
|
// Clocking
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.wr_i(wb_rd_write_w),
|
.wr_i(wb_rd_write_w),
|
|
|
// Tri-port
|
// Tri-port
|
.ra_i(dec_ra_w),
|
.ra_i(dec_ra_w),
|
.rb_i(dec_rb_w),
|
.rb_i(dec_rb_w),
|
.rd_i(wb_rd_w),
|
.rd_i(wb_rd_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rd_i(wb_rd_val_w)
|
.reg_rd_i(wb_rd_val_w)
|
);
|
);
|
end
|
end
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// [Altera] Register file
|
// [Altera] Register file
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else if (REGISTER_FILE_TYPE == "ALTERA")
|
else if (REGISTER_FILE_TYPE == "ALTERA")
|
begin : REGFILE_ALT
|
begin : REGFILE_ALT
|
altor32_regfile_alt
|
altor32_regfile_alt
|
#(
|
#(
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
)
|
)
|
u_regfile
|
u_regfile
|
(
|
(
|
// Clocking
|
// Clocking
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.wr_i(wb_rd_write_w),
|
.wr_i(wb_rd_write_w),
|
|
|
// Tri-port
|
// Tri-port
|
.ra_i(dec_ra_w),
|
.ra_i(dec_ra_w),
|
.rb_i(dec_rb_w),
|
.rb_i(dec_rb_w),
|
.rd_i(wb_rd_w),
|
.rd_i(wb_rd_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rd_i(wb_rd_val_w)
|
.reg_rd_i(wb_rd_val_w)
|
);
|
);
|
end
|
end
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// [Simulation] Register file
|
// [Simulation] Register file
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else
|
else
|
begin : REGFILE_SIM
|
begin : REGFILE_SIM
|
altor32_regfile_sim
|
altor32_regfile_sim
|
#(
|
#(
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
.SUPPORT_32REGS(SUPPORT_32REGS)
|
)
|
)
|
u_regfile
|
u_regfile
|
(
|
(
|
// Clocking
|
// Clocking
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.wr_i(wb_rd_write_w),
|
.wr_i(wb_rd_write_w),
|
|
|
// Tri-port
|
// Tri-port
|
.ra_i(dec_ra_w),
|
.ra_i(dec_ra_w),
|
.rb_i(dec_rb_w),
|
.rb_i(dec_rb_w),
|
.rd_i(wb_rd_w),
|
.rd_i(wb_rd_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_ra_o(dec_ra_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rb_o(dec_rb_val_w),
|
.reg_rd_i(wb_rd_val_w)
|
.reg_rd_i(wb_rd_val_w)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Data cache
|
// Data cache
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
generate
|
generate
|
if (ENABLE_DCACHE == "ENABLED")
|
if (ENABLE_DCACHE == "ENABLED")
|
begin : DCACHE
|
begin : DCACHE
|
altor32_dcache
|
altor32_dcache
|
u_dcache
|
u_dcache
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
.flush_i(dcache_flush_w),
|
.flush_i(dcache_flush_w),
|
|
|
// Processor interface
|
// Processor interface
|
.address_i({dcache_addr_w[31:2], 2'b00}),
|
.address_i({dcache_addr_w[31:2], 2'b00}),
|
.data_o(dcache_data_in_w),
|
.data_o(dcache_data_in_w),
|
.data_i(dcache_data_out_w),
|
.data_i(dcache_data_out_w),
|
.we_i(dcache_we_w),
|
.we_i(dcache_we_w),
|
.stb_i(dcache_stb_w),
|
.stb_i(dcache_stb_w),
|
.sel_i(dcache_sel_w),
|
.sel_i(dcache_sel_w),
|
.stall_o(dcache_stall_w),
|
.stall_o(dcache_stall_w),
|
.ack_o(dcache_ack_w),
|
.ack_o(dcache_ack_w),
|
|
|
// Memory interface (slave)
|
// Memory interface (slave)
|
.mem_addr_o(dmem_addr_o),
|
.mem_addr_o(dmem_addr_o),
|
.mem_data_i(dmem_dat_i),
|
.mem_data_i(dmem_dat_i),
|
.mem_data_o(dmem_dat_o),
|
.mem_data_o(dmem_dat_o),
|
.mem_sel_o(dmem_sel_o),
|
.mem_sel_o(dmem_sel_o),
|
.mem_we_o(dmem_we_o),
|
.mem_we_o(dmem_we_o),
|
.mem_stb_o(dmem_stb_o),
|
.mem_stb_o(dmem_stb_o),
|
.mem_cyc_o(dmem_cyc_o),
|
.mem_cyc_o(dmem_cyc_o),
|
.mem_cti_o(dmem_cti_o),
|
.mem_cti_o(dmem_cti_o),
|
.mem_stall_i(dmem_stall_i),
|
.mem_stall_i(dmem_stall_i),
|
.mem_ack_i(dmem_ack_i)
|
.mem_ack_i(dmem_ack_i)
|
);
|
);
|
end
|
end
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// No data cache
|
// No data cache
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
else
|
else
|
begin: NO_DCACHE
|
begin: NO_DCACHE
|
assign dmem_addr_o = {dcache_addr_w[31:2], 2'b00};
|
assign dmem_addr_o = {dcache_addr_w[31:2], 2'b00};
|
assign dmem_dat_o = dcache_data_out_w;
|
assign dmem_dat_o = dcache_data_out_w;
|
assign dcache_data_in_w = dmem_dat_i;
|
assign dcache_data_in_w = dmem_dat_i;
|
assign dmem_sel_o = dcache_sel_w;
|
assign dmem_sel_o = dcache_sel_w;
|
assign dmem_cyc_o = dcache_cyc_w;
|
assign dmem_cyc_o = dcache_cyc_w;
|
assign dmem_we_o = dcache_we_w;
|
assign dmem_we_o = dcache_we_w;
|
assign dmem_stb_o = dcache_stb_w;
|
assign dmem_stb_o = dcache_stb_w;
|
assign dmem_cti_o = 3'b111;
|
assign dmem_cti_o = 3'b111;
|
assign dcache_ack_w = dmem_ack_i;
|
assign dcache_ack_w = dmem_ack_i;
|
assign dcache_stall_w = dmem_stall_i;
|
assign dcache_stall_w = dmem_stall_i;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execution unit
|
// Execution unit
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
altor32_exec
|
altor32_exec
|
#(
|
#(
|
.BOOT_VECTOR(BOOT_VECTOR),
|
.BOOT_VECTOR(BOOT_VECTOR),
|
.ISR_VECTOR(ISR_VECTOR)
|
.ISR_VECTOR(ISR_VECTOR)
|
)
|
)
|
u_exec
|
u_exec
|
(
|
(
|
// General
|
// General
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
.intr_i(intr_i),
|
.intr_i(intr_i),
|
.nmi_i(nmi_i),
|
.break_i(nmi_i),
|
|
|
// Status
|
// Status
|
.fault_o(fault_o),
|
.fault_o(fault_o),
|
.break_o(break_o),
|
.break_o(break_o),
|
|
|
// Cache control
|
// Cache control
|
.icache_flush_o(icache_flush_w),
|
.icache_flush_o(icache_flush_w),
|
.dcache_flush_o(dcache_flush_w),
|
.dcache_flush_o(dcache_flush_w),
|
|
|
// Branch target
|
// Branch target
|
.branch_o(ex_branch_w),
|
.branch_o(ex_branch_w),
|
.branch_pc_o(ex_branch_pc_w),
|
.branch_pc_o(ex_branch_pc_w),
|
.stall_o(ex_stall_w),
|
.stall_o(ex_stall_w),
|
|
|
// Opcode & arguments
|
// Opcode & arguments
|
.opcode_i(dec_opcode_w),
|
.opcode_i(dec_opcode_w),
|
.opcode_pc_i(dec_opcode_pc_w),
|
.opcode_pc_i(dec_opcode_pc_w),
|
.opcode_valid_i(dec_opcode_valid_w),
|
.opcode_valid_i(dec_opcode_valid_w),
|
|
|
// Operands
|
// Operands
|
.reg_ra_i(dec_ra_w),
|
.reg_ra_i(dec_ra_w),
|
.reg_ra_value_i(dec_ra_val_w),
|
.reg_ra_value_i(dec_ra_val_w),
|
.reg_rb_i(dec_rb_w),
|
.reg_rb_i(dec_rb_w),
|
.reg_rb_value_i(dec_rb_val_w),
|
.reg_rb_value_i(dec_rb_val_w),
|
.reg_rd_i(dec_rd_w),
|
.reg_rd_i(dec_rd_w),
|
|
|
// Output
|
// Output
|
.opcode_o(ex_opcode_w),
|
.opcode_o(ex_opcode_w),
|
.opcode_pc_o(/* not used */),
|
.opcode_pc_o(/* not used */),
|
.reg_rd_o(ex_rd_w),
|
.reg_rd_o(ex_rd_w),
|
.reg_rd_value_o(ex_result_w),
|
.reg_rd_value_o(ex_result_w),
|
.mult_res_o(ex_mult_res_w),
|
.mult_res_o(ex_mult_res_w),
|
|
|
// Register write back bypass
|
// Register write back bypass
|
.wb_rd_i(wb_rd_w),
|
.wb_rd_i(wb_rd_w),
|
.wb_rd_value_i(wb_rd_val_w),
|
.wb_rd_value_i(wb_rd_val_w),
|
|
|
// Memory Interface
|
// Memory Interface
|
.dmem_addr_o(dcache_addr_w),
|
.dmem_addr_o(dcache_addr_w),
|
.dmem_data_out_o(dcache_data_out_w),
|
.dmem_data_out_o(dcache_data_out_w),
|
.dmem_data_in_i(dcache_data_in_w),
|
.dmem_data_in_i(dcache_data_in_w),
|
.dmem_sel_o(dcache_sel_w),
|
.dmem_sel_o(dcache_sel_w),
|
.dmem_we_o(dcache_we_w),
|
.dmem_we_o(dcache_we_w),
|
.dmem_stb_o(dcache_stb_w),
|
.dmem_stb_o(dcache_stb_w),
|
.dmem_cyc_o(dcache_cyc_w),
|
.dmem_cyc_o(dcache_cyc_w),
|
.dmem_stall_i(dcache_stall_w),
|
.dmem_stall_i(dcache_stall_w),
|
.dmem_ack_i(dcache_ack_w)
|
.dmem_ack_i(dcache_ack_w)
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Register file writeback
|
// Register file writeback
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
altor32_writeback
|
altor32_writeback
|
u_wb
|
u_wb
|
(
|
(
|
// General
|
// General
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
|
|
// Opcode
|
// Opcode
|
.opcode_i(ex_opcode_w),
|
.opcode_i(ex_opcode_w),
|
|
|
// Register target
|
// Register target
|
.rd_i(ex_rd_w),
|
.rd_i(ex_rd_w),
|
|
|
// ALU result
|
// ALU result
|
.alu_result_i(ex_result_w),
|
.alu_result_i(ex_result_w),
|
|
|
// Memory load result
|
// Memory load result
|
.mem_result_i(dcache_data_in_w),
|
.mem_result_i(dcache_data_in_w),
|
.mem_offset_i(dcache_addr_w[1:0]),
|
.mem_offset_i(dcache_addr_w[1:0]),
|
.mem_ready_i(dcache_ack_w),
|
.mem_ready_i(dcache_ack_w),
|
|
|
// Multiplier result
|
// Multiplier result
|
.mult_result_i(ex_mult_res_w),
|
.mult_result_i(ex_mult_res_w),
|
|
|
// Outputs
|
// Outputs
|
.write_enable_o(wb_rd_write_w),
|
.write_enable_o(wb_rd_write_w),
|
.write_addr_o(wb_rd_w),
|
.write_addr_o(wb_rd_w),
|
.write_data_o(wb_rd_val_w)
|
.write_data_o(wb_rd_val_w)
|
);
|
);
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
// Hooks for debug
|
// Hooks for debug
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
`ifdef verilator
|
`ifdef verilator
|
function [31:0] get_pc;
|
function [31:0] get_pc;
|
// verilator public
|
// verilator public
|
get_pc = dec_opcode_pc_w;
|
get_pc = dec_opcode_pc_w;
|
endfunction
|
endfunction
|
function get_fault;
|
function get_fault;
|
// verilator public
|
// verilator public
|
get_fault = fault_o;
|
get_fault = fault_o;
|
endfunction
|
endfunction
|
function get_break;
|
function get_break;
|
// verilator public
|
// verilator public
|
get_break = break_o;
|
get_break = break_o;
|
endfunction
|
endfunction
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|