| Line 1... |
Line 1... |
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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| Line 89... |
Line 89... |
parameter CACHE_TAG_DIRTY_BIT = 14;
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parameter CACHE_TAG_DIRTY_BIT = 14;
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parameter CACHE_TAG_VALID_BIT = 15;
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parameter CACHE_TAG_VALID_BIT = 15;
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parameter ADDR_NO_CACHE_BIT = 25;
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parameter ADDR_NO_CACHE_BIT = 25;
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parameter ADDR_CACHE_BYPASS_BIT = 31;
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parameter ADDR_CACHE_BYPASS_BIT = 31;
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parameter FLUSH_INITIAL = 0;
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// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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// |--------------| | | | | | | | | | | | | | | | |
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// |--------------| | | | | | | | | | | | | | | | |
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// +--------------------+ +-------------------+ +-----------+
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// +--------------------+ +-------------------+ +-----------+
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// Tag entry Line address Address
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// Tag entry Line address Address
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// (15-bits) (8-bits) within line
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// (15-bits) (8-bits) within line
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| Line 131... |
Line 133... |
reg req_ack;
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reg req_ack;
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reg [31:0] req_address;
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reg [31:0] req_address;
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reg [31:0] req_data;
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reg [31:0] req_data;
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reg req_flush;
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reg req_flush;
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reg req_init;
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reg flush_single;
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reg flush_single;
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wire [31:0] line_address;
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wire [31:0] line_address;
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wire [31:0] muxed_address = (state == STATE_IDLE) ? address_i : req_address;
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wire [31:0] muxed_address = (state == STATE_IDLE) ? address_i : req_address;
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| Line 158... |
Line 161... |
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assign tag_entry = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign tag_entry = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign cache_address = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
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assign cache_address = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
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assign data_o = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
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assign data_o = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
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assign stall_o = (state != STATE_IDLE) | req_flush;
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assign stall_o = (state != STATE_IDLE) | req_flush | flush_i;
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wire valid = tag_data_out[CACHE_TAG_VALID_BIT];
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wire valid = tag_data_out[CACHE_TAG_VALID_BIT];
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wire dirty = tag_data_out[CACHE_TAG_DIRTY_BIT];
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wire dirty = tag_data_out[CACHE_TAG_DIRTY_BIT];
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// Access is cacheable?
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// Access is cacheable?
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| Line 174... |
Line 177... |
// Cache hit?
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// Cache hit?
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wire hit = cacheable & valid & addr_hit & (state == STATE_CHECK);
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wire hit = cacheable & valid & addr_hit & (state == STATE_CHECK);
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assign ack_o = ack | hit;
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assign ack_o = ack | hit;
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assign line_address[31:CACHE_TAG_ADDR_HIGH+1] = {(31-CACHE_TAG_ADDR_HIGH){1'b0}};
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assign line_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] = tag_entry;
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assign line_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] = tag_entry;
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assign line_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] = tag_data_out[13:0];
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assign line_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] = tag_data_out[13:0];
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assign line_address[CACHE_LINE_SIZE_WIDTH-1:0] = {CACHE_LINE_SIZE_WIDTH{1'b0}};
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assign line_address[CACHE_LINE_SIZE_WIDTH-1:0] = {CACHE_LINE_SIZE_WIDTH{1'b0}};
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// Only allow cache write when same line present in the write state
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wire cache_wr_enable = (state == STATE_WRITE) ? valid & addr_hit : 1'b1;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Next State Logic
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// Next State Logic
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [3:0] next_state_r;
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reg [3:0] next_state_r;
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| Line 210... |
Line 216... |
// Write (cacheable)
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// Write (cacheable)
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else if (stb_i & we_i)
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else if (stb_i & we_i)
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next_state_r = STATE_WRITE;
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next_state_r = STATE_WRITE;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// WRITE - Wait for write-thru to complete
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// WRITE
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE :
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STATE_WRITE :
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begin
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begin
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// Cache hit
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// Cache hit (line already dirty)
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if (valid & addr_hit)
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if (valid & addr_hit & dirty)
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next_state_r = STATE_IDLE;
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// Cache hit, make line dirty
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else if (valid & addr_hit & ~dirty)
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next_state_r = STATE_WAIT2;
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next_state_r = STATE_WAIT2;
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// Cache dirty
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// Cache dirty
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else if (valid & dirty)
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else if (valid & dirty)
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next_state_r = STATE_EVICTING;
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next_state_r = STATE_EVICTING;
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// Cache miss
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// Cache miss
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| Line 341... |
Line 350... |
// FLUSH3 - Check if line dirty & flush
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// FLUSH3 - Check if line dirty & flush
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//-----------------------------------------
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//-----------------------------------------
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STATE_FLUSH3 :
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STATE_FLUSH3 :
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begin
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begin
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// Dirty line? Evict line first
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// Dirty line? Evict line first
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if (dirty)
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if (dirty && ~req_init)
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next_state_r = STATE_FLUSH4;
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next_state_r = STATE_FLUSH4;
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// Not dirty? Just invalidate
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// Not dirty? Just invalidate
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else
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else
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begin
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begin
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if (flush_single)
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if (flush_single)
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| Line 397... |
Line 406... |
begin
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begin
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tag_wr <= 1'b0;
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tag_wr <= 1'b0;
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case (state)
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// WRITE - Wait for write-thru to complete
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// WRITE
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE :
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STATE_WRITE :
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begin
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begin
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// Cache hit
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// Cache hit
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if (valid & addr_hit)
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if (valid & addr_hit)
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begin
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begin
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// Mark line as dirty
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// Mark line as dirty
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if (~dirty)
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begin
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tag_data_in <= tag_data_out;
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tag_data_in <= tag_data_out;
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tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
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tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b1;
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tag_wr <= 1'b1;
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tag_wr <= 1'b1;
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end
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end
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end
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// Cache miss / cache line doesn't require write back
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// Cache miss / cache line doesn't require write back
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else if (~valid | ~dirty)
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else if (~valid | ~dirty)
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begin
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begin
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// Update tag memory with this line's details
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// Update tag memory with this line's details
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tag_data_in <= {1'b1, 1'b1, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
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tag_data_in <= {1'b1, 1'b1, req_address[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
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| Line 497... |
Line 509... |
// FLUSH3 - Check if line dirty & flush
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// FLUSH3 - Check if line dirty & flush
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//-----------------------------------------
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//-----------------------------------------
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STATE_FLUSH3 :
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STATE_FLUSH3 :
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begin
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begin
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// Not dirty? Just invalidate
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// Not dirty? Just invalidate
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if (~dirty)
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if (~dirty | req_init)
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begin
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begin
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tag_data_in <= tag_data_out;
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tag_data_in <= 16'b0;
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tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
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tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
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tag_wr <= 1'b1;
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tag_wr <= 1'b1;
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end
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end
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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| Line 513... |
Line 525... |
begin
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begin
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// Cache line filled?
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// Cache line filled?
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if (done)
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if (done)
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begin
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begin
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// Invalidate line
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// Invalidate line
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tag_data_in <= tag_data_out;
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tag_data_in <= 16'b0;
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tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
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tag_data_in[CACHE_TAG_VALID_BIT] <= 1'b0;
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tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b0;
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tag_data_in[CACHE_TAG_DIRTY_BIT] <= 1'b0;
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tag_wr <= 1'b1;
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tag_wr <= 1'b1;
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end
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end
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end
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end
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| Line 537... |
Line 549... |
req_address <= 32'h00000000;
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req_address <= 32'h00000000;
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req_data <= 32'h00000000;
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req_data <= 32'h00000000;
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req_ack <= 1'b0;
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req_ack <= 1'b0;
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req_wr <= 4'h0;
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req_wr <= 4'h0;
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req_rd <= 1'b0;
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req_rd <= 1'b0;
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req_flush <= 1'b0;
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req_flush <= 1'b1;
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req_init <= FLUSH_INITIAL;
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end
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end
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else
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else
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begin
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begin
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if (flush_i)
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if (flush_i)
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req_flush <= 1'b1;
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req_flush <= 1'b1;
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| Line 605... |
Line 618... |
STATE_FLUSH1 :
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STATE_FLUSH1 :
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begin
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begin
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if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})
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if (req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] == {CACHE_LINE_ADDR_WIDTH{1'b1}})
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begin
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begin
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req_ack <= 1'b0;
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req_ack <= 1'b0;
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req_init <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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// Increment flush line address
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// Increment flush line address
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req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] <=
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req_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] <=
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| Line 635... |
Line 649... |
begin
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begin
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cache_wr <= 4'b0;
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cache_wr <= 4'b0;
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case (state)
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// WRITE - Wait for write-thru to complete
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// IDLE
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE :
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STATE_IDLE:
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begin
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begin
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// Cache hit
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// Write (cacheable)
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if (valid & addr_hit)
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if (stb_i & we_i & cacheable & ~(flush_i | req_flush))
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begin
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begin
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// Update line already in cache
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// Early write which is gated on line match
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cache_data_w <= req_data;
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cache_data_w <= data_i;
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cache_wr <= req_wr;
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cache_wr <= sel_i;
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end
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end
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// UPDATE - Update fetched cache line
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// UPDATE - Update fetched cache line
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//-----------------------------------------
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//-----------------------------------------
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| Line 713... |
Line 727... |
// Perform write single
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// Perform write single
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wr_single <= sel_i;
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wr_single <= sel_i;
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end
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end
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// WRITE - Wait for write-thru to complete
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// WRITE
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE :
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STATE_WRITE :
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begin
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begin
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// Cache hit
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// Cache hit
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if (valid & addr_hit)
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if (valid & addr_hit)
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| Line 947... |
Line 961... |
(
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(
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.aclk_i(clk_i),
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.aclk_i(clk_i),
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.aadr_i(cache_address),
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.aadr_i(cache_address),
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.adat_o(cache_data_r[7:0]),
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.adat_o(cache_data_r[7:0]),
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.adat_i(cache_data_w[7:0]),
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.adat_i(cache_data_w[7:0]),
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.awr_i(cache_wr[0]),
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.awr_i(cache_wr[0] & cache_wr_enable),
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|
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.bclk_i(clk_i),
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.bclk_i(clk_i),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.bdat_o(cache_update_data_r[7:0]),
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.bdat_o(cache_update_data_r[7:0]),
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.bdat_i(cache_update_data_w[7:0]),
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.bdat_i(cache_update_data_w[7:0]),
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| Line 967... |
Line 981... |
(
|
(
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.aclk_i(clk_i),
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.aclk_i(clk_i),
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.aadr_i(cache_address),
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.aadr_i(cache_address),
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.adat_o(cache_data_r[15:8]),
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.adat_o(cache_data_r[15:8]),
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.adat_i(cache_data_w[15:8]),
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.adat_i(cache_data_w[15:8]),
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.awr_i(cache_wr[1]),
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.awr_i(cache_wr[1] & cache_wr_enable),
|
|
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.bclk_i(clk_i),
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.bclk_i(clk_i),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.bdat_o(cache_update_data_r[15:8]),
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.bdat_o(cache_update_data_r[15:8]),
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.bdat_i(cache_update_data_w[15:8]),
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.bdat_i(cache_update_data_w[15:8]),
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| Line 987... |
Line 1001... |
(
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(
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.aclk_i(clk_i),
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.aclk_i(clk_i),
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.aadr_i(cache_address),
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.aadr_i(cache_address),
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.adat_o(cache_data_r[23:16]),
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.adat_o(cache_data_r[23:16]),
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.adat_i(cache_data_w[23:16]),
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.adat_i(cache_data_w[23:16]),
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.awr_i(cache_wr[2]),
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.awr_i(cache_wr[2] & cache_wr_enable),
|
|
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.bclk_i(clk_i),
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.bclk_i(clk_i),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.bdat_o(cache_update_data_r[23:16]),
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.bdat_o(cache_update_data_r[23:16]),
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.bdat_i(cache_update_data_w[23:16]),
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.bdat_i(cache_update_data_w[23:16]),
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| Line 1007... |
Line 1021... |
(
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(
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.aclk_i(clk_i),
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.aclk_i(clk_i),
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.aadr_i(cache_address),
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.aadr_i(cache_address),
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.adat_o(cache_data_r[31:24]),
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.adat_o(cache_data_r[31:24]),
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.adat_i(cache_data_w[31:24]),
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.adat_i(cache_data_w[31:24]),
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.awr_i(cache_wr[3]),
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.awr_i(cache_wr[3] & cache_wr_enable),
|
|
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.bclk_i(clk_i),
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.bclk_i(clk_i),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.badr_i(cache_update_addr[CACHE_DWIDTH+2-1:2]),
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.bdat_o(cache_update_data_r[31:24]),
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.bdat_o(cache_update_data_r[31:24]),
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.bdat_i(cache_update_data_w[31:24]),
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.bdat_i(cache_update_data_w[31:24]),
|
