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https://opencores.org/ocsvn/altor32/altor32/trunk
[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache.v] - Diff between revs 37 and 45
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| Rev 37 |
Rev 45 |
| Line 138... |
Line 138... |
reg req_init;
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reg req_init;
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reg flush_single;
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reg flush_single;
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wire [31:0] line_address;
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wire [31:0] line_address;
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wire [31:0] muxed_address = (state == STATE_IDLE) ? address_i : req_address;
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// Current state
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// Current state
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parameter STATE_IDLE = 0;
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parameter STATE_IDLE = 0;
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parameter STATE_SINGLE = 1;
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parameter STATE_SINGLE = 1;
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parameter STATE_CHECK = 2;
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parameter STATE_CHECK = 2;
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parameter STATE_FETCH = 3;
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parameter STATE_FETCH = 3;
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| Line 157... |
Line 155... |
parameter STATE_FLUSH2 = 11;
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parameter STATE_FLUSH2 = 11;
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parameter STATE_FLUSH3 = 12;
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parameter STATE_FLUSH3 = 12;
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parameter STATE_FLUSH4 = 13;
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parameter STATE_FLUSH4 = 13;
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reg [3:0] state;
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reg [3:0] state;
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wire [31:0] muxed_address = (state == STATE_IDLE) ? address_i : req_address;
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assign tag_entry = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign tag_entry = muxed_address[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign cache_address = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
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assign cache_address = {tag_entry, muxed_address[CACHE_LINE_SIZE_WIDTH-1:2]};
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assign data_o = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
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assign data_o = (state == STATE_SINGLE_READY) ? data_r : cache_data_r;
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assign stall_o = (state != STATE_IDLE) | req_flush | flush_i;
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assign stall_o = (state != STATE_IDLE) | req_flush | flush_i;
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