//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
|
// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
|
// This source is distributed in the hope that it will be
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// details.
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// details.
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//
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//
|
// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, write to the
|
// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - Data Cache Memory Interface
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// Module - Data Cache Memory Interface
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
|
module altor32_dcache_mem_if
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module altor32_dcache_mem_if
|
(
|
(
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
|
|
|
// Cache interface
|
// Cache interface
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input [31:0] address_i /*verilator public*/,
|
input [31:0] address_i /*verilator public*/,
|
input [31:0] data_i /*verilator public*/,
|
input [31:0] data_i /*verilator public*/,
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output reg [31:0] data_o /*verilator public*/,
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output reg [31:0] data_o /*verilator public*/,
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input fill_i /*verilator public*/,
|
input fill_i /*verilator public*/,
|
input evict_i /*verilator public*/,
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input evict_i /*verilator public*/,
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input [31:0] evict_addr_i /*verilator public*/,
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input [31:0] evict_addr_i /*verilator public*/,
|
input rd_single_i /*verilator public*/,
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input rd_single_i /*verilator public*/,
|
input [3:0] wr_single_i /*verilator public*/,
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input [3:0] wr_single_i /*verilator public*/,
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output reg done_o /*verilator public*/,
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output reg done_o /*verilator public*/,
|
|
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// Cache memory (fill/evict)
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// Cache memory (fill/evict)
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output reg [31:2] cache_addr_o /*verilator public*/,
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output reg [31:2] cache_addr_o /*verilator public*/,
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output reg [31:0] cache_data_o /*verilator public*/,
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output reg [31:0] cache_data_o /*verilator public*/,
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input [31:0] cache_data_i /*verilator public*/,
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input [31:0] cache_data_i /*verilator public*/,
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output reg cache_wr_o /*verilator public*/,
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output reg cache_wr_o /*verilator public*/,
|
|
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// Memory interface (slave)
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// Memory interface (slave)
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output reg [31:0] mem_addr_o /*verilator public*/,
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output reg [31:0] mem_addr_o /*verilator public*/,
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input [31:0] mem_data_i /*verilator public*/,
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input [31:0] mem_data_i /*verilator public*/,
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output reg [31:0] mem_data_o /*verilator public*/,
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output reg [31:0] mem_data_o /*verilator public*/,
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output reg [2:0] mem_cti_o /*verilator public*/,
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output reg [2:0] mem_cti_o /*verilator public*/,
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output reg mem_cyc_o /*verilator public*/,
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output reg mem_cyc_o /*verilator public*/,
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output reg mem_stb_o /*verilator public*/,
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output reg mem_stb_o /*verilator public*/,
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output reg mem_we_o /*verilator public*/,
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output reg mem_we_o /*verilator public*/,
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output reg [3:0] mem_sel_o /*verilator public*/,
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output reg [3:0] mem_sel_o /*verilator public*/,
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input mem_stall_i/*verilator public*/,
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input mem_stall_i/*verilator public*/,
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input mem_ack_i/*verilator public*/
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input mem_ack_i/*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
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parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
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parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit -> 8 words */
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parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit -> 8 words */
|
|
|
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
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reg [31:CACHE_LINE_SIZE_WIDTH] line_address;
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reg [31:CACHE_LINE_SIZE_WIDTH] line_address;
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|
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] response_idx;
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] response_idx;
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|
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] request_idx;
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] request_idx;
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wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_request_idx = request_idx + 1'b1;
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wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_request_idx = request_idx + 1'b1;
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|
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] cache_idx;
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reg [CACHE_LINE_WORDS_IDX_MAX-1:0] cache_idx;
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wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_cache_idx = cache_idx + 1'b1;
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wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_cache_idx = cache_idx + 1'b1;
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|
|
|
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// Current state
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// Current state
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parameter STATE_IDLE = 0;
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parameter STATE_IDLE = 0;
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parameter STATE_FETCH = 1;
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parameter STATE_FETCH = 1;
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parameter STATE_WRITE_SETUP = 2;
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parameter STATE_WRITE_SETUP = 2;
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parameter STATE_WRITE = 3;
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parameter STATE_WRITE = 3;
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parameter STATE_WRITE_WAIT = 4;
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parameter STATE_WRITE_WAIT = 4;
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parameter STATE_MEM_SINGLE = 5;
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parameter STATE_MEM_SINGLE = 5;
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parameter STATE_FETCH_WAIT = 6;
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parameter STATE_FETCH_WAIT = 6;
|
|
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reg [3:0] state;
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reg [3:0] state;
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|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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// Next State Logic
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// Next State Logic
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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reg [3:0] next_state_r;
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reg [3:0] next_state_r;
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always @ *
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always @ *
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begin
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begin
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next_state_r = state;
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next_state_r = state;
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|
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case (state)
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// IDLE
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// IDLE
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//-----------------------------------------
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//-----------------------------------------
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STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
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// Perform cache evict (write)
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// Perform cache evict (write)
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if (evict_i)
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if (evict_i)
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next_state_r = STATE_WRITE_SETUP;
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next_state_r = STATE_WRITE_SETUP;
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// Perform cache fill (read)
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// Perform cache fill (read)
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else if (fill_i)
|
else if (fill_i)
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next_state_r = STATE_FETCH;
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next_state_r = STATE_FETCH;
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// Read/Write single
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// Read/Write single
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else if (rd_single_i | (|wr_single_i))
|
else if (rd_single_i | (|wr_single_i))
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next_state_r = STATE_MEM_SINGLE;
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next_state_r = STATE_MEM_SINGLE;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// FETCH - Fetch line from memory
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// FETCH - Fetch line from memory
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//-----------------------------------------
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//-----------------------------------------
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STATE_FETCH :
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STATE_FETCH :
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begin
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begin
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// Line fetch complete?
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// Line fetch complete?
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if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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next_state_r = STATE_FETCH_WAIT;
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next_state_r = STATE_FETCH_WAIT;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// FETCH_WAIT - Wait for read responses
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// FETCH_WAIT - Wait for read responses
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//-----------------------------------------
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//-----------------------------------------
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STATE_FETCH_WAIT:
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STATE_FETCH_WAIT:
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begin
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begin
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// Read from memory complete
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// Read from memory complete
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if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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next_state_r = STATE_IDLE;
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next_state_r = STATE_IDLE;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// WRITE_SETUP - Wait for data from cache
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// WRITE_SETUP - Wait for data from cache
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE_SETUP :
|
STATE_WRITE_SETUP :
|
next_state_r = STATE_WRITE;
|
next_state_r = STATE_WRITE;
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//-----------------------------------------
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//-----------------------------------------
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// WRITE - Write word to memory
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// WRITE - Write word to memory
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//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE :
|
STATE_WRITE :
|
begin
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begin
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// Line write complete?
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// Line write complete?
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if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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next_state_r = STATE_WRITE_WAIT;
|
next_state_r = STATE_WRITE_WAIT;
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// Fetch next word for line
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// Fetch next word for line
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else if (~mem_stall_i | ~mem_stb_o)
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else if (~mem_stall_i | ~mem_stb_o)
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next_state_r = STATE_WRITE_SETUP;
|
next_state_r = STATE_WRITE_SETUP;
|
end
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end
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//-----------------------------------------
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//-----------------------------------------
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// WRITE_WAIT - Wait for write to complete
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// WRITE_WAIT - Wait for write to complete
|
//-----------------------------------------
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//-----------------------------------------
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STATE_WRITE_WAIT:
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STATE_WRITE_WAIT:
|
begin
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begin
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// Write to memory complete
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// Write to memory complete
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if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
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next_state_r = STATE_IDLE;
|
next_state_r = STATE_IDLE;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// MEM_SINGLE - Single access to memory
|
// MEM_SINGLE - Single access to memory
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//-----------------------------------------
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//-----------------------------------------
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STATE_MEM_SINGLE:
|
STATE_MEM_SINGLE:
|
begin
|
begin
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// Data ready from memory?
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// Data ready from memory?
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if (mem_ack_i)
|
if (mem_ack_i)
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next_state_r = STATE_IDLE;
|
next_state_r = STATE_IDLE;
|
end
|
end
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default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
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end
|
|
|
// Update state
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// Update state
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
state <= STATE_IDLE;
|
state <= STATE_IDLE;
|
else
|
else
|
state <= next_state_r;
|
state <= next_state_r;
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Control logic
|
// Control logic
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
line_address <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
|
line_address <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
|
done_o <= 1'b0;
|
done_o <= 1'b0;
|
data_o <= 32'h00000000;
|
data_o <= 32'h00000000;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
done_o <= 1'b0;
|
done_o <= 1'b0;
|
|
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
// Perform cache evict (write)
|
// Perform cache evict (write)
|
if (evict_i)
|
if (evict_i)
|
line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
|
line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
|
// Perform cache fill (read)
|
// Perform cache fill (read)
|
else if (fill_i)
|
else if (fill_i)
|
line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
|
line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH/WRITE_WAIT - Wait for oustanding responses
|
// FETCH/WRITE_WAIT - Wait for oustanding responses
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE_WAIT,
|
STATE_WRITE_WAIT,
|
STATE_FETCH_WAIT:
|
STATE_FETCH_WAIT:
|
begin
|
begin
|
// Write to memory complete
|
// Write to memory complete
|
if (mem_ack_i)
|
if (mem_ack_i)
|
begin
|
begin
|
// Line write complete?
|
// Line write complete?
|
if (response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
done_o <= 1'b1;
|
done_o <= 1'b1;
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// MEM_SINGLE - Single access to memory
|
// MEM_SINGLE - Single access to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_MEM_SINGLE:
|
STATE_MEM_SINGLE:
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i)
|
if (mem_ack_i)
|
begin
|
begin
|
data_o <= mem_data_i;
|
data_o <= mem_data_i;
|
done_o <= 1'b1;
|
done_o <= 1'b1;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Cache Read / Write
|
// Cache Read / Write
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
cache_addr_o <= 30'h00000000;
|
cache_addr_o <= 30'h00000000;
|
cache_data_o <= 32'h00000000;
|
cache_data_o <= 32'h00000000;
|
cache_wr_o <= 1'b0;
|
cache_wr_o <= 1'b0;
|
|
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cache_wr_o <= 1'b0;
|
cache_wr_o <= 1'b0;
|
|
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
|
// Perform cache evict (write)
|
// Perform cache evict (write)
|
if (evict_i)
|
if (evict_i)
|
begin
|
begin
|
// Read data from cache
|
// Read data from cache
|
cache_addr_o <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_WORDS_IDX_MAX{1'b0}}};
|
cache_addr_o <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_WORDS_IDX_MAX{1'b0}}};
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch line from memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH,
|
STATE_FETCH,
|
STATE_FETCH_WAIT:
|
STATE_FETCH_WAIT:
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i)
|
if (mem_ack_i)
|
begin
|
begin
|
// Write data into cache
|
// Write data into cache
|
cache_addr_o <= {line_address, cache_idx};
|
cache_addr_o <= {line_address, cache_idx};
|
cache_data_o <= mem_data_i;
|
cache_data_o <= mem_data_i;
|
cache_wr_o <= 1'b1;
|
cache_wr_o <= 1'b1;
|
|
|
cache_idx <= next_cache_idx;
|
cache_idx <= next_cache_idx;
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE - Write word to memory
|
// WRITE - Write word to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE_SETUP:
|
STATE_WRITE_SETUP:
|
begin
|
begin
|
|
|
end
|
end
|
STATE_WRITE,
|
STATE_WRITE,
|
STATE_WRITE_WAIT:
|
STATE_WRITE_WAIT:
|
begin
|
begin
|
if (~mem_stall_i | ~mem_stb_o)
|
if (~mem_stall_i | ~mem_stb_o)
|
begin
|
begin
|
// Setup next word read from cache
|
// Setup next word read from cache
|
cache_addr_o <= {line_address, next_cache_idx};
|
cache_addr_o <= {line_address, next_cache_idx};
|
cache_idx <= next_cache_idx;
|
cache_idx <= next_cache_idx;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Request
|
// Request
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
mem_addr_o <= 32'h00000000;
|
mem_addr_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_sel_o <= 4'h0;
|
mem_sel_o <= 4'h0;
|
mem_cti_o <= 3'b0;
|
mem_cti_o <= 3'b0;
|
mem_stb_o <= 1'b0;
|
mem_stb_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (~mem_stall_i)
|
if (~mem_stall_i)
|
begin
|
begin
|
mem_stb_o <= 1'b0;
|
mem_stb_o <= 1'b0;
|
|
|
// TMP
|
// TMP
|
if (mem_cti_o == 3'b111)
|
if (mem_cti_o == 3'b111)
|
begin
|
begin
|
//mem_addr_o <= 32'h00000000;
|
//mem_addr_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_sel_o <= 4'h0;
|
mem_sel_o <= 4'h0;
|
mem_cti_o <= 3'b0;
|
mem_cti_o <= 3'b0;
|
mem_stb_o <= 1'b0;
|
mem_stb_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
|
// Perform cache evict (write)
|
// Perform cache evict (write)
|
if (evict_i)
|
if (evict_i)
|
begin
|
begin
|
|
|
end
|
end
|
// Perform cache fill (read)
|
// Perform cache fill (read)
|
else if (fill_i)
|
else if (fill_i)
|
begin
|
begin
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
mem_addr_o <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
mem_data_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_sel_o <= 4'b1111;
|
mem_sel_o <= 4'b1111;
|
mem_cti_o <= 3'b010;
|
mem_cti_o <= 3'b010;
|
mem_stb_o <= 1'b1;
|
mem_stb_o <= 1'b1;
|
mem_we_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
|
|
request_idx <= next_request_idx;
|
request_idx <= next_request_idx;
|
end
|
end
|
// Read single
|
// Read single
|
else if (rd_single_i)
|
else if (rd_single_i)
|
begin
|
begin
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= address_i;
|
mem_addr_o <= address_i;
|
mem_data_o <= 32'h00000000;
|
mem_data_o <= 32'h00000000;
|
mem_sel_o <= 4'b1111;
|
mem_sel_o <= 4'b1111;
|
mem_cti_o <= 3'b111;
|
mem_cti_o <= 3'b111;
|
mem_stb_o <= 1'b1;
|
mem_stb_o <= 1'b1;
|
mem_we_o <= 1'b0;
|
mem_we_o <= 1'b0;
|
end
|
end
|
// Write single
|
// Write single
|
else if (|wr_single_i)
|
else if (|wr_single_i)
|
begin
|
begin
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= address_i;
|
mem_addr_o <= address_i;
|
mem_data_o <= data_i;
|
mem_data_o <= data_i;
|
mem_sel_o <= wr_single_i;
|
mem_sel_o <= wr_single_i;
|
mem_cti_o <= 3'b111;
|
mem_cti_o <= 3'b111;
|
mem_stb_o <= 1'b1;
|
mem_stb_o <= 1'b1;
|
mem_we_o <= 1'b1;
|
mem_we_o <= 1'b1;
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch line from memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH :
|
STATE_FETCH :
|
begin
|
begin
|
// Previous request accepted?
|
// Previous request accepted?
|
if (~mem_stall_i)
|
if (~mem_stall_i)
|
begin
|
begin
|
// Fetch next word for line
|
// Fetch next word for line
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
mem_stb_o <= 1'b1;
|
mem_stb_o <= 1'b1;
|
|
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_cti_o <= 3'b111;
|
mem_cti_o <= 3'b111;
|
|
|
request_idx <= next_request_idx;
|
request_idx <= next_request_idx;
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE - Write word to memory
|
// WRITE - Write word to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE :
|
STATE_WRITE :
|
begin
|
begin
|
// Memory interface can request command?
|
// Memory interface can request command?
|
if (~mem_stall_i | ~mem_stb_o)
|
if (~mem_stall_i | ~mem_stb_o)
|
begin
|
begin
|
// Write data into memory from cache
|
// Write data into memory from cache
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
mem_data_o <= cache_data_i;
|
mem_data_o <= cache_data_i;
|
mem_sel_o <= 4'b1111;
|
mem_sel_o <= 4'b1111;
|
mem_stb_o <= 1'b1;
|
mem_stb_o <= 1'b1;
|
mem_we_o <= 1'b1;
|
mem_we_o <= 1'b1;
|
|
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_cti_o <= 3'b111;
|
mem_cti_o <= 3'b111;
|
else
|
else
|
mem_cti_o <= 3'b010;
|
mem_cti_o <= 3'b010;
|
|
|
request_idx <= next_request_idx;
|
request_idx <= next_request_idx;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Memory Response Counter
|
// Memory Response Counter
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
else
|
else
|
begin
|
begin
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch line from memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH,
|
STATE_FETCH,
|
STATE_FETCH_WAIT :
|
STATE_FETCH_WAIT :
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i)
|
if (mem_ack_i)
|
response_idx <= response_idx + 1'b1;
|
response_idx <= response_idx + 1'b1;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE_WAIT - Wait for write to complete
|
// WRITE_WAIT - Wait for write to complete
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE,
|
STATE_WRITE,
|
STATE_WRITE_SETUP,
|
STATE_WRITE_SETUP,
|
STATE_WRITE_WAIT:
|
STATE_WRITE_WAIT:
|
begin
|
begin
|
// Write to memory complete
|
// Write to memory complete
|
if (mem_ack_i)
|
if (mem_ack_i)
|
response_idx <= response_idx + 1'b1;
|
response_idx <= response_idx + 1'b1;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// CYC_O
|
// CYC_O
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
mem_cyc_o <= 1'b0;
|
mem_cyc_o <= 1'b0;
|
else
|
else
|
begin
|
begin
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
// Perform cache evict (write)
|
// Perform cache evict (write)
|
if (evict_i)
|
if (evict_i)
|
begin
|
begin
|
|
|
end
|
end
|
// Perform cache fill (read)
|
// Perform cache fill (read)
|
else if (fill_i)
|
else if (fill_i)
|
mem_cyc_o <= 1'b1;
|
mem_cyc_o <= 1'b1;
|
// Read single
|
// Read single
|
else if (rd_single_i)
|
else if (rd_single_i)
|
mem_cyc_o <= 1'b1;
|
mem_cyc_o <= 1'b1;
|
// Write single
|
// Write single
|
else if (|wr_single_i)
|
else if (|wr_single_i)
|
mem_cyc_o <= 1'b1;
|
mem_cyc_o <= 1'b1;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch line from memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH :
|
STATE_FETCH :
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_cyc_o <= 1'b0;
|
mem_cyc_o <= 1'b0;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE - Write word to memory
|
// WRITE - Write word to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE :
|
STATE_WRITE :
|
begin
|
begin
|
// Write data into memory from cache
|
// Write data into memory from cache
|
mem_cyc_o <= 1'b1;
|
mem_cyc_o <= 1'b1;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH/WRITE_WAIT - Wait for responses
|
// FETCH/WRITE_WAIT - Wait for responses
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE_WAIT,
|
STATE_WRITE_WAIT,
|
STATE_FETCH_WAIT:
|
STATE_FETCH_WAIT:
|
begin
|
begin
|
// Write to memory complete
|
// Write to memory complete
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_cyc_o <= 1'b0;
|
mem_cyc_o <= 1'b0;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// MEM_SINGLE - Single access to memory
|
// MEM_SINGLE - Single access to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_MEM_SINGLE:
|
STATE_MEM_SINGLE:
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i)
|
if (mem_ack_i)
|
mem_cyc_o <= 1'b0;
|
mem_cyc_o <= 1'b0;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
