//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.0
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2013
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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|
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//`define CONF_CORE_DEBUG
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//`define CONF_CORE_DEBUG
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//`define CONF_CORE_DEBUG_BUBBLE
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|
//`define CONF_CORE_TRACE
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//`define CONF_CORE_TRACE
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//`define CONF_CORE_FAULT_ON_OPCODE0
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|
|
|
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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// Includes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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`include "altor32_defs.v"
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|
|
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - Instruction Execute
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// Module - Instruction Execute
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module altor32_exec
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module altor32_exec
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(
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(
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// General
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// General
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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|
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// Maskable interrupt
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// Maskable interrupt
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input intr_i /*verilator public*/,
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input intr_i /*verilator public*/,
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|
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// Unmaskable interrupt
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// Unmaskable interrupt
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input nmi_i /*verilator public*/,
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input nmi_i /*verilator public*/,
|
|
|
// Fault
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// Fault
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output reg fault_o /*verilator public*/,
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output reg fault_o /*verilator public*/,
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|
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// Breakpoint / Trap
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// Breakpoint / Trap
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output reg break_o /*verilator public*/,
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output reg break_o /*verilator public*/,
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|
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// Cache control
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// Cache control
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output reg icache_flush_o /*verilator public*/,
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output reg icache_flush_o /*verilator public*/,
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output reg dcache_flush_o /*verilator public*/,
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output reg dcache_flush_o /*verilator public*/,
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|
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// Branch
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// Branch
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output branch_o /*verilator public*/,
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output branch_o /*verilator public*/,
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output [31:0] branch_pc_o /*verilator public*/,
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output [31:0] branch_pc_o /*verilator public*/,
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output stall_o /*verilator public*/,
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output stall_o /*verilator public*/,
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|
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// Opcode & arguments
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// Opcode & arguments
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input [31:0] opcode_i /*verilator public*/,
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input [31:0] opcode_i /*verilator public*/,
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input [31:0] opcode_pc_i /*verilator public*/,
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input [31:0] opcode_pc_i /*verilator public*/,
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input opcode_valid_i /*verilator public*/,
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input opcode_valid_i /*verilator public*/,
|
|
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// Reg A
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// Reg A
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input [4:0] reg_ra_i /*verilator public*/,
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input [4:0] reg_ra_i /*verilator public*/,
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input [31:0] reg_ra_value_i /*verilator public*/,
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input [31:0] reg_ra_value_i /*verilator public*/,
|
|
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// Reg B
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// Reg B
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input [4:0] reg_rb_i /*verilator public*/,
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input [4:0] reg_rb_i /*verilator public*/,
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input [31:0] reg_rb_value_i /*verilator public*/,
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input [31:0] reg_rb_value_i /*verilator public*/,
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|
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// Reg D
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// Reg D
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input [4:0] reg_rd_i /*verilator public*/,
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input [4:0] reg_rd_i /*verilator public*/,
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|
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// Output
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// Output
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output [31:0] opcode_o /*verilator public*/,
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output [31:0] opcode_o /*verilator public*/,
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output [4:0] reg_rd_o /*verilator public*/,
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output [4:0] reg_rd_o /*verilator public*/,
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output [31:0] reg_rd_value_o /*verilator public*/,
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output [31:0] reg_rd_value_o /*verilator public*/,
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output mult_o /*verilator public*/,
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output mult_o /*verilator public*/,
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output [31:0] mult_res_o /*verilator public*/,
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output [31:0] mult_res_o /*verilator public*/,
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|
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// Register write back bypass
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// Register write back bypass
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input [4:0] wb_rd_i /*verilator public*/,
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input [4:0] wb_rd_i /*verilator public*/,
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input [31:0] wb_rd_value_i /*verilator public*/,
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input [31:0] wb_rd_value_i /*verilator public*/,
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|
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// Memory Interface
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// Memory Interface
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output reg [31:0] dmem_addr_o /*verilator public*/,
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output reg [31:0] dmem_addr_o /*verilator public*/,
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output reg [31:0] dmem_data_out_o /*verilator public*/,
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output reg [31:0] dmem_data_out_o /*verilator public*/,
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input [31:0] dmem_data_in_i /*verilator public*/,
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input [31:0] dmem_data_in_i /*verilator public*/,
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output reg [3:0] dmem_wr_o /*verilator public*/,
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output reg [3:0] dmem_sel_o /*verilator public*/,
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output reg dmem_rd_o /*verilator public*/,
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output reg dmem_we_o /*verilator public*/,
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input dmem_accept_i /*verilator public*/,
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output reg dmem_stb_o /*verilator public*/,
|
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output reg dmem_cyc_o /*verilator public*/,
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input dmem_stall_i /*verilator public*/,
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input dmem_ack_i /*verilator public*/
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input dmem_ack_i /*verilator public*/
|
);
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);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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// Params
|
// Params
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
parameter BOOT_VECTOR = 32'h00000000;
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parameter BOOT_VECTOR = 32'h00000000;
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parameter ISR_VECTOR = 32'h00000000;
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parameter ISR_VECTOR = 32'h00000000;
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
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// Branch PC
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// Branch PC
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reg [31:0] r_pc_branch;
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reg [31:0] r_pc_branch;
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reg r_pc_fetch;
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reg r_pc_fetch;
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reg r_stall;
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reg r_stall;
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|
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// Exception saved program counter
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// Exception saved program counter
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reg [31:0] r_epc;
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reg [31:0] r_epc;
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|
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// Supervisor register
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// Supervisor register
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reg [31:0] r_sr;
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reg [31:0] r_sr;
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|
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// Exception saved supervisor register
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// Exception saved supervisor register
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reg [31:0] r_esr;
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reg [31:0] r_esr;
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|
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// Destination register number (post execute stage)
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// Destination register number (post execute stage)
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reg [4:0] r_e_rd;
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reg [4:0] r_e_rd;
|
|
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// Current opcode (PC for debug)
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// Current opcode (PC for debug)
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reg [31:0] r_e_opcode;
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reg [31:0] r_e_opcode;
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reg [31:0] r_e_opcode_pc;
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reg [31:0] r_e_opcode_pc;
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|
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// ALU input A
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// ALU input A
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reg [31:0] r_e_alu_a;
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reg [31:0] r_e_alu_a;
|
|
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// ALU input B
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// ALU input B
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reg [31:0] r_e_alu_b;
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reg [31:0] r_e_alu_b;
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|
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// ALU output
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// ALU output
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wire [31:0] r_e_result;
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wire [31:0] r_e_result;
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|
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// Resolved RA/RB register contents
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// Resolved RA/RB register contents
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wire [31:0] ra_value_resolved;
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wire [31:0] ra_value_resolved;
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wire [31:0] rb_value_resolved;
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wire [31:0] rb_value_resolved;
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wire resolve_failed;
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wire resolve_failed;
|
|
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// ALU Carry
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// ALU Carry
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wire alu_carry_out;
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wire alu_carry_out;
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wire alu_carry_update;
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wire alu_carry_update;
|
|
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// ALU operation selection
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// ALU operation selection
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reg [3:0] r_e_alu_func;
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reg [3:0] r_e_alu_func;
|
|
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// Load instruction details
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// Load instruction details
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reg [4:0] r_load_rd;
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reg [4:0] r_load_rd;
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reg [7:0] r_load_inst;
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reg [7:0] r_load_inst;
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reg [1:0] r_load_offset;
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reg [1:0] r_load_offset;
|
|
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// Load forwarding
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// Load forwarding
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wire load_insn;
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wire load_insn;
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wire [31:0] load_result;
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wire [31:0] load_result;
|
|
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// Memory access?
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// Memory access?
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reg r_mem_load;
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reg r_mem_load;
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reg r_mem_store;
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reg r_mem_store;
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reg r_mem_access;
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reg r_mem_access;
|
|
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wire load_pending;
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wire load_pending;
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wire store_pending;
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wire store_pending;
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wire load_insert;
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wire load_insert;
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wire load_stall;
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wire load_stall;
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|
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reg d_mem_load;
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reg d_mem_load;
|
|
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// Delayed NMI
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// Delayed NMI
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reg r_nmi;
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reg r_nmi;
|
|
|
// SIM PUTC
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// SIM PUTC
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`ifdef SIM_EXT_PUTC
|
`ifdef SIM_EXT_PUTC
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reg [7:0] r_putc;
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reg [7:0] r_putc;
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`endif
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`endif
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|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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// Instantiation
|
// Instantiation
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// ALU
|
// ALU
|
altor32_alu alu
|
altor32_alu alu
|
(
|
(
|
// ALU operation select
|
// ALU operation select
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.op_i(r_e_alu_func),
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.op_i(r_e_alu_func),
|
|
|
// Operands
|
// Operands
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.a_i(r_e_alu_a),
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.a_i(r_e_alu_a),
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.b_i(r_e_alu_b),
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.b_i(r_e_alu_b),
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.c_i(r_sr[`OR32_SR_CY]),
|
.c_i(r_sr[`OR32_SR_CY]),
|
|
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// Result
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// Result
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.p_o(r_e_result),
|
.p_o(r_e_result),
|
|
|
// Carry
|
// Carry
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.c_o(alu_carry_out),
|
.c_o(alu_carry_out),
|
.c_update_o(alu_carry_update)
|
.c_update_o(alu_carry_update)
|
);
|
);
|
|
|
// Load result forwarding
|
// Load result forwarding
|
altor32_lfu
|
altor32_lfu
|
u_lfu
|
u_lfu
|
(
|
(
|
// Opcode
|
// Opcode
|
.opcode_i(r_load_inst),
|
.opcode_i(r_load_inst),
|
|
|
// Memory load result
|
// Memory load result
|
.mem_result_i(dmem_data_in_i),
|
.mem_result_i(dmem_data_in_i),
|
.mem_offset_i(r_load_offset),
|
.mem_offset_i(r_load_offset),
|
|
|
// Result
|
// Result
|
.load_result_o(load_result),
|
.load_result_o(load_result),
|
.load_insn_o(load_insn)
|
.load_insn_o(load_insn)
|
);
|
);
|
|
|
// Load / store pending logic
|
// Load / store pending logic
|
altor32_lsu
|
altor32_lsu
|
u_lsu
|
u_lsu
|
(
|
(
|
// Current instruction
|
// Current instruction
|
.opcode_valid_i(opcode_valid_i & ~r_pc_fetch),
|
.opcode_valid_i(opcode_valid_i & ~r_pc_fetch),
|
.opcode_i({2'b00,opcode_i[31:26]}),
|
.opcode_i({2'b00,opcode_i[31:26]}),
|
|
|
// Load / Store pending
|
// Load / Store pending
|
.load_pending_i(r_mem_load),
|
.load_pending_i(r_mem_load),
|
.store_pending_i(r_mem_store),
|
.store_pending_i(r_mem_store),
|
|
|
// Load dest register
|
// Load dest register
|
.rd_load_i(r_load_rd),
|
.rd_load_i(r_load_rd),
|
|
|
// Load insn in WB stage
|
// Load insn in WB stage
|
.load_wb_i(d_mem_load),
|
.load_wb_i(d_mem_load),
|
|
|
// Memory status
|
// Memory status
|
.mem_access_i(r_mem_access),
|
.mem_access_i(r_mem_access),
|
.mem_ack_i(dmem_ack_i),
|
.mem_ack_i(dmem_ack_i),
|
|
|
// Load / store still pending
|
// Load / store still pending
|
.load_pending_o(load_pending),
|
.load_pending_o(load_pending),
|
.store_pending_o(store_pending),
|
.store_pending_o(store_pending),
|
|
|
// Insert load result into pipeline
|
// Insert load result into pipeline
|
.write_result_o(load_insert),
|
.write_result_o(load_insert),
|
|
|
// Stall pipeline due
|
// Stall pipeline due
|
.stall_o(load_stall)
|
.stall_o(load_stall)
|
);
|
);
|
|
|
// Operand forwarding
|
// Operand forwarding
|
altor32_dfu
|
altor32_dfu
|
u_dfu
|
u_dfu
|
(
|
(
|
// Input registers
|
// Input registers
|
.ra_i(reg_ra_i),
|
.ra_i(reg_ra_i),
|
.rb_i(reg_rb_i),
|
.rb_i(reg_rb_i),
|
|
|
// Input register contents
|
// Input register contents
|
.ra_regval_i(reg_ra_value_i),
|
.ra_regval_i(reg_ra_value_i),
|
.rb_regval_i(reg_rb_value_i),
|
.rb_regval_i(reg_rb_value_i),
|
|
|
// Dest register (EXEC stage)
|
// Dest register (EXEC stage)
|
.rd_ex_i(r_e_rd),
|
.rd_ex_i(r_e_rd),
|
|
|
// Dest register (WB stage)
|
// Dest register (WB stage)
|
.rd_wb_i(wb_rd_i),
|
.rd_wb_i(wb_rd_i),
|
|
|
// Load pending / target
|
// Load pending / target
|
.load_pending_i(load_pending),
|
.load_pending_i(load_pending),
|
.rd_load_i(r_load_rd),
|
.rd_load_i(r_load_rd),
|
|
|
// Multiplier status
|
// Multiplier status
|
.mult_lo_ex_i(1'b0),
|
.mult_lo_ex_i(1'b0),
|
.mult_hi_ex_i(1'b0),
|
.mult_hi_ex_i(1'b0),
|
.mult_lo_wb_i(1'b0),
|
.mult_lo_wb_i(1'b0),
|
.mult_hi_wb_i(1'b0),
|
.mult_hi_wb_i(1'b0),
|
|
|
// Multiplier result
|
// Multiplier result
|
.result_mult_i(64'b0),
|
.result_mult_i(64'b0),
|
|
|
// Result (EXEC)
|
// Result (EXEC)
|
.result_ex_i(r_e_result),
|
.result_ex_i(r_e_result),
|
|
|
// Result (WB)
|
// Result (WB)
|
.result_wb_i(wb_rd_value_i),
|
.result_wb_i(wb_rd_value_i),
|
|
|
// Resolved register values
|
// Resolved register values
|
.result_ra_o(ra_value_resolved),
|
.result_ra_o(ra_value_resolved),
|
.result_rb_o(rb_value_resolved),
|
.result_rb_o(rb_value_resolved),
|
|
|
// Stall due to failed resolve
|
// Stall due to failed resolve
|
.stall_o(resolve_failed)
|
.stall_o(resolve_failed)
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Opcode decode
|
// Opcode decode
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [7:0] inst_r;
|
reg [7:0] inst_r;
|
reg [7:0] alu_op_r;
|
reg [7:0] alu_op_r;
|
reg [1:0] shift_op_r;
|
reg [1:0] shift_op_r;
|
reg [15:0] sfxx_op_r;
|
reg [15:0] sfxx_op_r;
|
reg [15:0] uint16_r;
|
reg [15:0] uint16_r;
|
reg [31:0] uint32_r;
|
reg [31:0] uint32_r;
|
reg [31:0] int32_r;
|
reg [31:0] int32_r;
|
reg [31:0] store_int32_r;
|
reg [31:0] store_int32_r;
|
reg [15:0] mxspr_uint16_r;
|
reg [15:0] mxspr_uint16_r;
|
reg [31:0] target_int26_r;
|
reg [31:0] target_int26_r;
|
reg [31:0] reg_ra_r;
|
reg [31:0] reg_ra_r;
|
reg [31:0] reg_rb_r;
|
reg [31:0] reg_rb_r;
|
reg [31:0] shift_rb_r;
|
reg [31:0] shift_rb_r;
|
reg [31:0] shift_imm_r;
|
reg [31:0] shift_imm_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
// Instruction
|
// Instruction
|
inst_r = {2'b00,opcode_i[31:26]};
|
inst_r = {2'b00,opcode_i[31:26]};
|
|
|
// Sub instructions
|
// Sub instructions
|
alu_op_r = {opcode_i[9:6],opcode_i[3:0]};
|
alu_op_r = {opcode_i[9:6],opcode_i[3:0]};
|
sfxx_op_r = {5'b00,opcode_i[31:21]};
|
sfxx_op_r = {5'b00,opcode_i[31:21]};
|
shift_op_r = opcode_i[7:6];
|
shift_op_r = opcode_i[7:6];
|
|
|
// Branch target
|
// Branch target
|
target_int26_r = sign_extend_imm26(opcode_i[25:0]);
|
target_int26_r = sign_extend_imm26(opcode_i[25:0]);
|
|
|
// Store immediate
|
// Store immediate
|
store_int32_r = sign_extend_imm16({opcode_i[25:21],opcode_i[10:0]});
|
store_int32_r = sign_extend_imm16({opcode_i[25:21],opcode_i[10:0]});
|
|
|
// Signed & unsigned imm -> 32-bits
|
// Signed & unsigned imm -> 32-bits
|
uint16_r = opcode_i[15:0];
|
uint16_r = opcode_i[15:0];
|
int32_r = sign_extend_imm16(opcode_i[15:0]);
|
int32_r = sign_extend_imm16(opcode_i[15:0]);
|
uint32_r = extend_imm16(opcode_i[15:0]);
|
uint32_r = extend_imm16(opcode_i[15:0]);
|
|
|
// Register values [ra/rb]
|
// Register values [ra/rb]
|
reg_ra_r = ra_value_resolved;
|
reg_ra_r = ra_value_resolved;
|
reg_rb_r = rb_value_resolved;
|
reg_rb_r = rb_value_resolved;
|
|
|
// Shift ammount (from register[rb])
|
// Shift ammount (from register[rb])
|
shift_rb_r = {26'b00,rb_value_resolved[5:0]};
|
shift_rb_r = {26'b00,rb_value_resolved[5:0]};
|
|
|
// Shift ammount (from immediate)
|
// Shift ammount (from immediate)
|
shift_imm_r = {26'b00,opcode_i[5:0]};
|
shift_imm_r = {26'b00,opcode_i[5:0]};
|
|
|
// MTSPR/MFSPR operand
|
// MTSPR/MFSPR operand
|
mxspr_uint16_r = (ra_value_resolved[15:0] | {5'b00000,opcode_i[10:0]});
|
mxspr_uint16_r = (ra_value_resolved[15:0] | {5'b00000,opcode_i[10:0]});
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Instruction Decode
|
// Instruction Decode
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
wire inst_add_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_ADD); // l.add
|
wire inst_add_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_ADD); // l.add
|
wire inst_addc_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_ADDC); // l.addc
|
wire inst_addc_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_ADDC); // l.addc
|
wire inst_and_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_AND); // l.and
|
wire inst_and_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_AND); // l.and
|
wire inst_or_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_OR); // l.or
|
wire inst_or_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_OR); // l.or
|
wire inst_sll_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SLL); // l.sll
|
wire inst_sll_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SLL); // l.sll
|
wire inst_sra_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SRA); // l.sra
|
wire inst_sra_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SRA); // l.sra
|
wire inst_srl_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SRL); // l.srl
|
wire inst_srl_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SRL); // l.srl
|
wire inst_sub_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SUB); // l.sub
|
wire inst_sub_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_SUB); // l.sub
|
wire inst_xor_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_XOR); // l.xor
|
wire inst_xor_w = (inst_r == `INST_OR32_ALU) & (alu_op_r == `INST_OR32_XOR); // l.xor
|
|
|
wire inst_addi_w = (inst_r == `INST_OR32_ADDI); // l.addi
|
wire inst_addi_w = (inst_r == `INST_OR32_ADDI); // l.addi
|
wire inst_andi_w = (inst_r == `INST_OR32_ANDI); // l.andi
|
wire inst_andi_w = (inst_r == `INST_OR32_ANDI); // l.andi
|
wire inst_bf_w = (inst_r == `INST_OR32_BF); // l.bf
|
wire inst_bf_w = (inst_r == `INST_OR32_BF); // l.bf
|
wire inst_bnf_w = (inst_r == `INST_OR32_BNF); // l.bnf
|
wire inst_bnf_w = (inst_r == `INST_OR32_BNF); // l.bnf
|
wire inst_j_w = (inst_r == `INST_OR32_J); // l.j
|
wire inst_j_w = (inst_r == `INST_OR32_J); // l.j
|
wire inst_jal_w = (inst_r == `INST_OR32_JAL); // l.jal
|
wire inst_jal_w = (inst_r == `INST_OR32_JAL); // l.jal
|
wire inst_jalr_w = (inst_r == `INST_OR32_JALR); // l.jalr
|
wire inst_jalr_w = (inst_r == `INST_OR32_JALR); // l.jalr
|
wire inst_jr_w = (inst_r == `INST_OR32_JR); // l.jr
|
wire inst_jr_w = (inst_r == `INST_OR32_JR); // l.jr
|
wire inst_lbs_w = (inst_r == `INST_OR32_LBS); // l.lbs
|
wire inst_lbs_w = (inst_r == `INST_OR32_LBS); // l.lbs
|
wire inst_lhs_w = (inst_r == `INST_OR32_LHS); // l.lhs
|
wire inst_lhs_w = (inst_r == `INST_OR32_LHS); // l.lhs
|
wire inst_lws_w = (inst_r == `INST_OR32_LWS); // l.lws
|
wire inst_lws_w = (inst_r == `INST_OR32_LWS); // l.lws
|
wire inst_lbz_w = (inst_r == `INST_OR32_LBZ); // l.lbz
|
wire inst_lbz_w = (inst_r == `INST_OR32_LBZ); // l.lbz
|
wire inst_lhz_w = (inst_r == `INST_OR32_LHZ); // l.lhz
|
wire inst_lhz_w = (inst_r == `INST_OR32_LHZ); // l.lhz
|
wire inst_lwz_w = (inst_r == `INST_OR32_LWZ); // l.lwz
|
wire inst_lwz_w = (inst_r == `INST_OR32_LWZ); // l.lwz
|
wire inst_mfspr_w = (inst_r == `INST_OR32_MFSPR); // l.mfspr
|
wire inst_mfspr_w = (inst_r == `INST_OR32_MFSPR); // l.mfspr
|
wire inst_mtspr_w = (inst_r == `INST_OR32_MTSPR); // l.mtspr
|
wire inst_mtspr_w = (inst_r == `INST_OR32_MTSPR); // l.mtspr
|
wire inst_movhi_w = (inst_r == `INST_OR32_MOVHI); // l.movhi
|
wire inst_movhi_w = (inst_r == `INST_OR32_MOVHI); // l.movhi
|
wire inst_nop_w = (inst_r == `INST_OR32_NOP); // l.nop
|
wire inst_nop_w = (inst_r == `INST_OR32_NOP); // l.nop
|
wire inst_ori_w = (inst_r == `INST_OR32_ORI); // l.ori
|
wire inst_ori_w = (inst_r == `INST_OR32_ORI); // l.ori
|
wire inst_rfe_w = (inst_r == `INST_OR32_RFE); // l.rfe
|
wire inst_rfe_w = (inst_r == `INST_OR32_RFE); // l.rfe
|
|
|
wire inst_sb_w = (inst_r == `INST_OR32_SB); // l.sb
|
wire inst_sb_w = (inst_r == `INST_OR32_SB); // l.sb
|
wire inst_sh_w = (inst_r == `INST_OR32_SH); // l.sh
|
wire inst_sh_w = (inst_r == `INST_OR32_SH); // l.sh
|
wire inst_sw_w = (inst_r == `INST_OR32_SW); // l.sw
|
wire inst_sw_w = (inst_r == `INST_OR32_SW); // l.sw
|
|
|
wire inst_slli_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SLLI); // l.slli
|
wire inst_slli_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SLLI); // l.slli
|
wire inst_srai_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SRAI); // l.srai
|
wire inst_srai_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SRAI); // l.srai
|
wire inst_srli_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SRLI); // l.srli
|
wire inst_srli_w = (inst_r == `INST_OR32_SHIFTI) & (shift_op_r == `INST_OR32_SRLI); // l.srli
|
|
|
wire inst_xori_w = (inst_r == `INST_OR32_XORI); // l.xori
|
wire inst_xori_w = (inst_r == `INST_OR32_XORI); // l.xori
|
|
|
wire inst_sfxx_w = (inst_r == `INST_OR32_SFXX);
|
wire inst_sfxx_w = (inst_r == `INST_OR32_SFXX);
|
wire inst_sfxxi_w = (inst_r == `INST_OR32_SFXXI);
|
wire inst_sfxxi_w = (inst_r == `INST_OR32_SFXXI);
|
|
|
wire inst_sfeq_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFEQ); // l.sfeq
|
wire inst_sfeq_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFEQ); // l.sfeq
|
wire inst_sfges_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGES); // l.sfges
|
wire inst_sfges_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGES); // l.sfges
|
|
|
wire inst_sfgeu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGEU); // l.sfgeu
|
wire inst_sfgeu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGEU); // l.sfgeu
|
wire inst_sfgts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTS); // l.sfgts
|
wire inst_sfgts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTS); // l.sfgts
|
wire inst_sfgtu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTU); // l.sfgtu
|
wire inst_sfgtu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFGTU); // l.sfgtu
|
wire inst_sfles_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLES); // l.sfles
|
wire inst_sfles_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLES); // l.sfles
|
wire inst_sfleu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLEU); // l.sfleu
|
wire inst_sfleu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLEU); // l.sfleu
|
wire inst_sflts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTS); // l.sflts
|
wire inst_sflts_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTS); // l.sflts
|
wire inst_sfltu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTU); // l.sfltu
|
wire inst_sfltu_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFLTU); // l.sfltu
|
wire inst_sfne_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFNE); // l.sfne
|
wire inst_sfne_w = (inst_r == `INST_OR32_SFXX) & (sfxx_op_r == `INST_OR32_SFNE); // l.sfne
|
|
|
wire inst_sfeqi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFEQI); // l.sfeqi
|
wire inst_sfeqi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFEQI); // l.sfeqi
|
wire inst_sfgesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGESI); // l.sfgesi
|
wire inst_sfgesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGESI); // l.sfgesi
|
wire inst_sfgeui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGEUI); // l.sfgeui
|
wire inst_sfgeui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGEUI); // l.sfgeui
|
wire inst_sfgtsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTSI); // l.sfgtsi
|
wire inst_sfgtsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTSI); // l.sfgtsi
|
wire inst_sfgtui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTUI); // l.sfgtui
|
wire inst_sfgtui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFGTUI); // l.sfgtui
|
wire inst_sflesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLESI); // l.sflesi
|
wire inst_sflesi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLESI); // l.sflesi
|
|
|
wire inst_sfleui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLEUI); // l.sfleui
|
wire inst_sfleui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLEUI); // l.sfleui
|
wire inst_sfltsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTSI); // l.sfltsi
|
wire inst_sfltsi_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTSI); // l.sfltsi
|
wire inst_sfltui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTUI); // l.sfltui
|
wire inst_sfltui_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFLTUI); // l.sfltui
|
wire inst_sfnei_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFNEI); // l.sfnei
|
wire inst_sfnei_w = (inst_r == `INST_OR32_SFXXI) & (sfxx_op_r == `INST_OR32_SFNEI); // l.sfnei
|
|
|
wire inst_sys_w = (inst_r == `INST_OR32_MISC) & (opcode_i[31:24] == `INST_OR32_SYS); // l.sys
|
wire inst_sys_w = (inst_r == `INST_OR32_MISC) & (opcode_i[31:24] == `INST_OR32_SYS); // l.sys
|
wire inst_trap_w = (inst_r == `INST_OR32_MISC) & (opcode_i[31:24] == `INST_OR32_TRAP); // l.trap
|
wire inst_trap_w = (inst_r == `INST_OR32_MISC) & (opcode_i[31:24] == `INST_OR32_TRAP); // l.trap
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Stall / Execute
|
// Stall / Execute
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg execute_inst_r;
|
reg execute_inst_r;
|
reg stall_inst_r;
|
reg stall_inst_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
execute_inst_r = 1'b1;
|
execute_inst_r = 1'b1;
|
stall_inst_r = 1'b0;
|
stall_inst_r = 1'b0;
|
|
|
// No opcode ready or branch delay slot
|
// No opcode ready or branch delay slot
|
if (~opcode_valid_i | r_pc_fetch)
|
if (~opcode_valid_i | r_pc_fetch)
|
execute_inst_r = 1'b0;
|
execute_inst_r = 1'b0;
|
// Valid instruction, but load result / operand not ready
|
// Valid instruction, but load result / operand not ready
|
else if (resolve_failed | load_stall)
|
else if (resolve_failed | load_stall)
|
stall_inst_r = 1'b1;
|
stall_inst_r = 1'b1;
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Next PC
|
// Next PC
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [31:0] next_pc_r;
|
reg [31:0] next_pc_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
// Next expected PC (current PC + 4)
|
// Next expected PC (current PC + 4)
|
next_pc_r = (opcode_pc_i + 4);
|
next_pc_r = (opcode_pc_i + 4);
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Next SR
|
// Next SR
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [31:0] next_sr_r;
|
reg [31:0] next_sr_r;
|
reg compare_result_r;
|
reg compare_result_r;
|
always @ *
|
always @ *
|
begin
|
begin
|
next_sr_r = r_sr;
|
next_sr_r = r_sr;
|
|
|
// Latch carry if updated
|
// Latch carry if updated
|
if (alu_carry_update)
|
if (alu_carry_update)
|
next_sr_r[`OR32_SR_CY] = alu_carry_out;
|
next_sr_r[`OR32_SR_CY] = alu_carry_out;
|
|
|
// If valid instruction, check if SR needs updating
|
// If valid instruction, check if SR needs updating
|
if (execute_inst_r & ~stall_inst_r)
|
if (execute_inst_r & ~stall_inst_r)
|
begin
|
begin
|
case (1'b1)
|
case (1'b1)
|
inst_mtspr_w:
|
inst_mtspr_w:
|
begin
|
begin
|
case (mxspr_uint16_r)
|
case (mxspr_uint16_r)
|
// SR - Supervision register
|
// SR - Supervision register
|
`SPR_REG_SR:
|
`SPR_REG_SR:
|
begin
|
begin
|
next_sr_r = reg_rb_r;
|
next_sr_r = reg_rb_r;
|
|
|
// Don't store cache flush requests
|
// Don't store cache flush requests
|
next_sr_r[`OR32_SR_ICACHE_FLUSH] = 1'b0;
|
next_sr_r[`OR32_SR_ICACHE_FLUSH] = 1'b0;
|
next_sr_r[`OR32_SR_DCACHE_FLUSH] = 1'b0;
|
next_sr_r[`OR32_SR_DCACHE_FLUSH] = 1'b0;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
inst_rfe_w:
|
inst_rfe_w:
|
next_sr_r = r_esr;
|
next_sr_r = r_esr;
|
inst_sfxx_w,
|
inst_sfxx_w,
|
inst_sfxxi_w:
|
inst_sfxxi_w:
|
next_sr_r[`OR32_SR_F] = compare_result_r;
|
next_sr_r[`OR32_SR_F] = compare_result_r;
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Next EPC/ESR
|
// Next EPC/ESR
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [31:0] next_epc_r;
|
reg [31:0] next_epc_r;
|
reg [31:0] next_esr_r;
|
reg [31:0] next_esr_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
next_epc_r = r_epc;
|
next_epc_r = r_epc;
|
next_esr_r = r_esr;
|
next_esr_r = r_esr;
|
|
|
case (1'b1)
|
case (1'b1)
|
inst_mtspr_w: // l.mtspr
|
inst_mtspr_w: // l.mtspr
|
begin
|
begin
|
case (mxspr_uint16_r)
|
case (mxspr_uint16_r)
|
// EPCR - EPC Exception saved PC
|
// EPCR - EPC Exception saved PC
|
`SPR_REG_EPCR: next_epc_r = reg_rb_r;
|
`SPR_REG_EPCR: next_epc_r = reg_rb_r;
|
|
|
// ESR - Exception saved SR
|
// ESR - Exception saved SR
|
`SPR_REG_ESR: next_esr_r = reg_rb_r;
|
`SPR_REG_ESR: next_esr_r = reg_rb_r;
|
endcase
|
endcase
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// ALU inputs
|
// ALU inputs
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// ALU operation selection
|
// ALU operation selection
|
reg [3:0] alu_func_r;
|
reg [3:0] alu_func_r;
|
|
|
// ALU operands
|
// ALU operands
|
reg [31:0] alu_input_a_r;
|
reg [31:0] alu_input_a_r;
|
reg [31:0] alu_input_b_r;
|
reg [31:0] alu_input_b_r;
|
reg write_rd_r;
|
reg write_rd_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
alu_func_r = `ALU_NONE;
|
alu_func_r = `ALU_NONE;
|
alu_input_a_r = 32'b0;
|
alu_input_a_r = 32'b0;
|
alu_input_b_r = 32'b0;
|
alu_input_b_r = 32'b0;
|
write_rd_r = 1'b0;
|
write_rd_r = 1'b0;
|
|
|
case (1'b1)
|
case (1'b1)
|
|
|
inst_add_w: // l.add
|
inst_add_w: // l.add
|
begin
|
begin
|
alu_func_r = `ALU_ADD;
|
alu_func_r = `ALU_ADD;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_addc_w: // l.addc
|
inst_addc_w: // l.addc
|
begin
|
begin
|
alu_func_r = `ALU_ADDC;
|
alu_func_r = `ALU_ADDC;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_and_w: // l.and
|
inst_and_w: // l.and
|
begin
|
begin
|
alu_func_r = `ALU_AND;
|
alu_func_r = `ALU_AND;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_or_w: // l.or
|
inst_or_w: // l.or
|
begin
|
begin
|
alu_func_r = `ALU_OR;
|
alu_func_r = `ALU_OR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_sll_w: // l.sll
|
inst_sll_w: // l.sll
|
begin
|
begin
|
alu_func_r = `ALU_SHIFTL;
|
alu_func_r = `ALU_SHIFTL;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_rb_r;
|
alu_input_b_r = shift_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_sra_w: // l.sra
|
inst_sra_w: // l.sra
|
begin
|
begin
|
alu_func_r = `ALU_SHIRTR_ARITH;
|
alu_func_r = `ALU_SHIRTR_ARITH;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_rb_r;
|
alu_input_b_r = shift_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_srl_w: // l.srl
|
inst_srl_w: // l.srl
|
begin
|
begin
|
alu_func_r = `ALU_SHIFTR;
|
alu_func_r = `ALU_SHIFTR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_rb_r;
|
alu_input_b_r = shift_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_sub_w: // l.sub
|
inst_sub_w: // l.sub
|
begin
|
begin
|
alu_func_r = `ALU_SUB;
|
alu_func_r = `ALU_SUB;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_xor_w: // l.xor
|
inst_xor_w: // l.xor
|
begin
|
begin
|
alu_func_r = `ALU_XOR;
|
alu_func_r = `ALU_XOR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = reg_rb_r;
|
alu_input_b_r = reg_rb_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_addi_w: // l.addi
|
inst_addi_w: // l.addi
|
begin
|
begin
|
alu_func_r = `ALU_ADD;
|
alu_func_r = `ALU_ADD;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = int32_r;
|
alu_input_b_r = int32_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_andi_w: // l.andi
|
inst_andi_w: // l.andi
|
begin
|
begin
|
alu_func_r = `ALU_AND;
|
alu_func_r = `ALU_AND;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = uint32_r;
|
alu_input_b_r = uint32_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_jal_w: // l.jal
|
inst_jal_w: // l.jal
|
begin
|
begin
|
alu_input_a_r = next_pc_r;
|
alu_input_a_r = next_pc_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_jalr_w: // l.jalr
|
inst_jalr_w: // l.jalr
|
begin
|
begin
|
alu_input_a_r = next_pc_r;
|
alu_input_a_r = next_pc_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_mfspr_w: // l.mfspr
|
inst_mfspr_w: // l.mfspr
|
begin
|
begin
|
case (mxspr_uint16_r)
|
case (mxspr_uint16_r)
|
// SR - Supervision register
|
// SR - Supervision register
|
`SPR_REG_SR:
|
`SPR_REG_SR:
|
begin
|
begin
|
alu_input_a_r = next_sr_r;
|
alu_input_a_r = next_sr_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
// EPCR - EPC Exception saved PC
|
// EPCR - EPC Exception saved PC
|
`SPR_REG_EPCR:
|
`SPR_REG_EPCR:
|
begin
|
begin
|
alu_input_a_r = r_epc;
|
alu_input_a_r = r_epc;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
// ESR - Exception saved SR
|
// ESR - Exception saved SR
|
`SPR_REG_ESR:
|
`SPR_REG_ESR:
|
begin
|
begin
|
alu_input_a_r = r_esr;
|
alu_input_a_r = r_esr;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_movhi_w: // l.movhi
|
inst_movhi_w: // l.movhi
|
begin
|
begin
|
alu_input_a_r = {uint16_r,16'h0000};
|
alu_input_a_r = {uint16_r,16'h0000};
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_ori_w: // l.ori
|
inst_ori_w: // l.ori
|
begin
|
begin
|
alu_func_r = `ALU_OR;
|
alu_func_r = `ALU_OR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = uint32_r;
|
alu_input_b_r = uint32_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_slli_w: // l.slli
|
inst_slli_w: // l.slli
|
begin
|
begin
|
alu_func_r = `ALU_SHIFTL;
|
alu_func_r = `ALU_SHIFTL;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_imm_r;
|
alu_input_b_r = shift_imm_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_srai_w: // l.srai
|
inst_srai_w: // l.srai
|
begin
|
begin
|
alu_func_r = `ALU_SHIRTR_ARITH;
|
alu_func_r = `ALU_SHIRTR_ARITH;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_imm_r;
|
alu_input_b_r = shift_imm_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
inst_srli_w: // l.srli
|
inst_srli_w: // l.srli
|
begin
|
begin
|
alu_func_r = `ALU_SHIFTR;
|
alu_func_r = `ALU_SHIFTR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = shift_imm_r;
|
alu_input_b_r = shift_imm_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
|
|
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
|
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
|
inst_lbs_w,
|
inst_lbs_w,
|
inst_lhs_w,
|
inst_lhs_w,
|
inst_lws_w,
|
inst_lws_w,
|
inst_lbz_w,
|
inst_lbz_w,
|
inst_lhz_w,
|
inst_lhz_w,
|
inst_lwz_w:
|
inst_lwz_w:
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
|
|
inst_xori_w: // l.xori
|
inst_xori_w: // l.xori
|
begin
|
begin
|
alu_func_r = `ALU_XOR;
|
alu_func_r = `ALU_XOR;
|
alu_input_a_r = reg_ra_r;
|
alu_input_a_r = reg_ra_r;
|
alu_input_b_r = int32_r;
|
alu_input_b_r = int32_r;
|
write_rd_r = 1'b1;
|
write_rd_r = 1'b1;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Comparisons
|
// Comparisons
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
reg [31:0] compare_a_r;
|
|
reg [31:0] compare_b_r;
|
always @ *
|
always @ *
|
begin
|
begin
|
compare_result_r = 1'b0;
|
compare_a_r = reg_ra_r;
|
|
compare_b_r = reg_rb_r;
|
|
|
case (1'b1)
|
case (1'b1)
|
inst_sfeq_w: // l.sfeq
|
inst_sfeqi_w, // l.sfeqi
|
begin
|
inst_sfgesi_w, // l.sfgesi
|
if (reg_ra_r == reg_rb_r)
|
inst_sfgeui_w, // l.sfgeui
|
compare_result_r = 1'b1;
|
inst_sfgtsi_w, // l.sfgtsi
|
else
|
inst_sfgtui_w, // l.sfgtui
|
compare_result_r = 1'b0;
|
inst_sflesi_w, // l.sflesi
|
|
inst_sfleui_w, // l.sfleui
|
|
inst_sfltsi_w, // l.sfltsi
|
|
inst_sfltui_w, // l.sfltui
|
|
inst_sfnei_w: // l.sfnei
|
|
compare_b_r = int32_r;
|
|
default:
|
|
;
|
|
endcase
|
end
|
end
|
|
|
inst_sfeqi_w: // l.sfeqi
|
reg compare_equal_r;
|
|
reg compare_gts_r;
|
|
reg compare_gt_r;
|
|
reg compare_lts_r;
|
|
reg compare_lt_r;
|
|
always @ *
|
begin
|
begin
|
if (reg_ra_r == int32_r)
|
if (compare_a_r == compare_b_r)
|
compare_result_r = 1'b1;
|
compare_equal_r = 1'b1;
|
else
|
else
|
compare_result_r = 1'b0;
|
compare_equal_r = 1'b0;
|
end
|
|
|
|
inst_sfges_w: // l.sfges
|
compare_lts_r = less_than_signed(compare_a_r, compare_b_r);
|
begin
|
|
if (greater_than_equal_signed(reg_ra_r, reg_rb_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfgesi_w: // l.sfgesi
|
if (compare_a_r < compare_b_r)
|
begin
|
compare_lt_r = 1'b1;
|
if (greater_than_equal_signed(reg_ra_r, int32_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
else
|
compare_result_r = 1'b0;
|
compare_lt_r = 1'b0;
|
end
|
|
|
|
inst_sfgeu_w: // l.sfgeu
|
// Greater than (signed)
|
begin
|
compare_gts_r = ~(compare_lts_r | compare_equal_r);
|
if (reg_ra_r >= reg_rb_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfgeui_w: // l.sfgeui
|
if (compare_a_r > compare_b_r)
|
begin
|
compare_gt_r = 1'b1;
|
if (reg_ra_r >= int32_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
else
|
compare_result_r = 1'b0;
|
compare_gt_r = 1'b0;
|
end
|
end
|
|
|
inst_sfgts_w: // l.sfgts
|
always @ *
|
begin
|
begin
|
if (greater_than_signed(reg_ra_r, reg_rb_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
compare_result_r = 1'b0;
|
end
|
|
|
|
inst_sfgtsi_w: // l.sfgtsi
|
case (1'b1)
|
begin
|
inst_sfeq_w, // l.sfeq
|
if (greater_than_signed(reg_ra_r, int32_r) == 1'b1)
|
inst_sfeqi_w: // l.sfeqi
|
compare_result_r = 1'b1;
|
compare_result_r = compare_equal_r;
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfgtu_w: // l.sfgtu
|
inst_sfges_w, // l.sfges
|
begin
|
inst_sfgesi_w: // l.sfgesi
|
if (reg_ra_r > reg_rb_r)
|
compare_result_r = compare_gts_r | compare_equal_r;
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfgtui_w: // l.sfgtui
|
inst_sfgeu_w, // l.sfgeu
|
begin
|
inst_sfgeui_w: // l.sfgeui
|
if (reg_ra_r > int32_r)
|
compare_result_r = compare_gt_r | compare_equal_r;
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfles_w: // l.sfles
|
inst_sfgts_w, // l.sfgts
|
begin
|
inst_sfgtsi_w: // l.sfgtsi
|
if (less_than_equal_signed(reg_ra_r, reg_rb_r) == 1'b1)
|
compare_result_r = compare_gts_r;
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
|
inst_sfgtu_w, // l.sfgtu
|
|
inst_sfgtui_w: // l.sfgtui
|
|
compare_result_r = compare_gt_r;
|
|
|
|
inst_sfles_w, // l.sfles
|
inst_sflesi_w: // l.sflesi
|
inst_sflesi_w: // l.sflesi
|
begin
|
compare_result_r = compare_lts_r | compare_equal_r;
|
if (less_than_equal_signed(reg_ra_r, int32_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfleu_w: // l.sfleu
|
inst_sfleu_w, // l.sfleu
|
begin
|
|
if (reg_ra_r <= reg_rb_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfleui_w: // l.sfleui
|
inst_sfleui_w: // l.sfleui
|
begin
|
compare_result_r = compare_lt_r | compare_equal_r;
|
if (reg_ra_r <= int32_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sflts_w: // l.sflts
|
inst_sflts_w, // l.sflts
|
begin
|
|
if (less_than_signed(reg_ra_r, reg_rb_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfltsi_w: // l.sfltsi
|
inst_sfltsi_w: // l.sfltsi
|
begin
|
compare_result_r = compare_lts_r;
|
if (less_than_signed(reg_ra_r, int32_r) == 1'b1)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfltu_w: // l.sfltu
|
inst_sfltu_w, // l.sfltu
|
begin
|
|
if (reg_ra_r < reg_rb_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfltui_w: // l.sfltui
|
inst_sfltui_w: // l.sfltui
|
begin
|
compare_result_r = compare_lt_r;
|
if (reg_ra_r < int32_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfne_w: // l.sfne
|
inst_sfne_w, // l.sfne
|
begin
|
|
if (reg_ra_r != reg_rb_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
|
|
inst_sfnei_w: // l.sfnei
|
inst_sfnei_w: // l.sfnei
|
begin
|
compare_result_r = ~compare_equal_r;
|
if (reg_ra_r != int32_r)
|
|
compare_result_r = 1'b1;
|
|
else
|
|
compare_result_r = 1'b0;
|
|
end
|
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Load/Store operation?
|
// Load/Store operation?
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg load_inst_r;
|
reg load_inst_r;
|
reg store_inst_r;
|
reg store_inst_r;
|
reg [31:0] mem_addr_r;
|
reg [31:0] mem_addr_r;
|
always @ *
|
always @ *
|
begin
|
begin
|
load_inst_r = inst_lbs_w | inst_lhs_w | inst_lws_w |
|
load_inst_r = inst_lbs_w | inst_lhs_w | inst_lws_w |
|
inst_lbz_w | inst_lhz_w | inst_lwz_w;
|
inst_lbz_w | inst_lhz_w | inst_lwz_w;
|
store_inst_r = inst_sb_w | inst_sh_w | inst_sw_w;
|
store_inst_r = inst_sb_w | inst_sh_w | inst_sw_w;
|
|
|
// Memory address is relative to RA
|
// Memory address is relative to RA
|
mem_addr_r = reg_ra_r + (store_inst_r ? store_int32_r : int32_r);
|
mem_addr_r = reg_ra_r + (store_inst_r ? store_int32_r : int32_r);
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Branches
|
// Branches
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg branch_r;
|
reg branch_r;
|
reg branch_link_r;
|
reg branch_link_r;
|
reg [31:0] branch_target_r;
|
reg [31:0] branch_target_r;
|
reg branch_except_r;
|
reg branch_except_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
|
|
branch_r = 1'b0;
|
branch_r = 1'b0;
|
branch_link_r = 1'b0;
|
branch_link_r = 1'b0;
|
branch_except_r = 1'b0;
|
branch_except_r = 1'b0;
|
|
|
// Default branch target is relative to current PC
|
// Default branch target is relative to current PC
|
branch_target_r = (opcode_pc_i + {target_int26_r[29:0],2'b00});
|
branch_target_r = (opcode_pc_i + {target_int26_r[29:0],2'b00});
|
|
|
case (1'b1)
|
case (1'b1)
|
inst_bf_w: // l.bf
|
inst_bf_w: // l.bf
|
branch_r = r_sr[`OR32_SR_F];
|
branch_r = r_sr[`OR32_SR_F];
|
|
|
inst_bnf_w: // l.bnf
|
inst_bnf_w: // l.bnf
|
branch_r = ~r_sr[`OR32_SR_F];
|
branch_r = ~r_sr[`OR32_SR_F];
|
|
|
inst_j_w: // l.j
|
inst_j_w: // l.j
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
|
|
inst_jal_w: // l.jal
|
inst_jal_w: // l.jal
|
begin
|
begin
|
// Write to REG_9_LR
|
// Write to REG_9_LR
|
branch_link_r = 1'b1;
|
branch_link_r = 1'b1;
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
end
|
end
|
|
|
inst_jalr_w: // l.jalr
|
inst_jalr_w: // l.jalr
|
begin
|
begin
|
// Write to REG_9_LR
|
// Write to REG_9_LR
|
branch_link_r = 1'b1;
|
branch_link_r = 1'b1;
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
branch_target_r = reg_rb_r;
|
branch_target_r = reg_rb_r;
|
end
|
end
|
|
|
inst_jr_w: // l.jr
|
inst_jr_w: // l.jr
|
begin
|
begin
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
branch_target_r = reg_rb_r;
|
branch_target_r = reg_rb_r;
|
end
|
end
|
|
|
inst_rfe_w: // l.rfe
|
inst_rfe_w: // l.rfe
|
begin
|
begin
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
branch_target_r = r_epc;
|
branch_target_r = r_epc;
|
end
|
end
|
|
|
inst_sys_w: // l.sys
|
inst_sys_w: // l.sys
|
begin
|
begin
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
branch_except_r = 1'b1;
|
branch_except_r = 1'b1;
|
branch_target_r = ISR_VECTOR + `VECTOR_SYSCALL;
|
branch_target_r = ISR_VECTOR + `VECTOR_SYSCALL;
|
end
|
end
|
|
|
inst_trap_w: // l.trap
|
inst_trap_w: // l.trap
|
begin
|
begin
|
branch_r = 1'b1;
|
branch_r = 1'b1;
|
branch_except_r = 1'b1;
|
branch_except_r = 1'b1;
|
branch_target_r = ISR_VECTOR + `VECTOR_TRAP;
|
branch_target_r = ISR_VECTOR + `VECTOR_TRAP;
|
end
|
end
|
|
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Invalid instruction
|
// Invalid instruction
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg invalid_inst_r;
|
reg invalid_inst_r;
|
|
|
always @ *
|
always @ *
|
begin
|
begin
|
case (1'b1)
|
case (1'b1)
|
inst_add_w,
|
inst_add_w,
|
inst_addc_w,
|
inst_addc_w,
|
inst_and_w,
|
inst_and_w,
|
inst_or_w,
|
inst_or_w,
|
inst_sll_w,
|
inst_sll_w,
|
inst_sra_w,
|
inst_sra_w,
|
inst_srl_w,
|
inst_srl_w,
|
inst_sub_w,
|
inst_sub_w,
|
inst_xor_w,
|
inst_xor_w,
|
inst_addi_w,
|
inst_addi_w,
|
inst_andi_w,
|
inst_andi_w,
|
inst_bf_w,
|
inst_bf_w,
|
inst_bnf_w,
|
inst_bnf_w,
|
inst_j_w,
|
inst_j_w,
|
inst_jal_w,
|
inst_jal_w,
|
inst_jalr_w,
|
inst_jalr_w,
|
inst_jr_w,
|
inst_jr_w,
|
inst_lbs_w,
|
inst_lbs_w,
|
inst_lhs_w,
|
inst_lhs_w,
|
inst_lws_w,
|
inst_lws_w,
|
inst_lbz_w,
|
inst_lbz_w,
|
inst_lhz_w,
|
inst_lhz_w,
|
inst_lwz_w,
|
inst_lwz_w,
|
inst_mfspr_w,
|
inst_mfspr_w,
|
inst_mtspr_w,
|
inst_mtspr_w,
|
inst_movhi_w,
|
inst_movhi_w,
|
inst_nop_w,
|
inst_nop_w,
|
inst_ori_w,
|
inst_ori_w,
|
inst_rfe_w,
|
inst_rfe_w,
|
inst_sb_w,
|
inst_sb_w,
|
inst_sh_w,
|
inst_sh_w,
|
inst_sw_w,
|
inst_sw_w,
|
inst_xori_w,
|
inst_xori_w,
|
inst_slli_w,
|
inst_slli_w,
|
inst_srai_w,
|
inst_srai_w,
|
inst_srli_w,
|
inst_srli_w,
|
inst_sfeq_w,
|
inst_sfeq_w,
|
inst_sfeqi_w,
|
inst_sfeqi_w,
|
inst_sfges_w,
|
inst_sfges_w,
|
inst_sfgesi_w,
|
inst_sfgesi_w,
|
inst_sfgeu_w,
|
inst_sfgeu_w,
|
inst_sfgeui_w,
|
inst_sfgeui_w,
|
inst_sfgts_w,
|
inst_sfgts_w,
|
inst_sfgtsi_w,
|
inst_sfgtsi_w,
|
inst_sfgtu_w,
|
inst_sfgtu_w,
|
inst_sfgtui_w,
|
inst_sfgtui_w,
|
inst_sfles_w,
|
inst_sfles_w,
|
inst_sflesi_w,
|
inst_sflesi_w,
|
inst_sfleu_w,
|
inst_sfleu_w,
|
inst_sfleui_w,
|
inst_sfleui_w,
|
inst_sflts_w,
|
inst_sflts_w,
|
inst_sfltsi_w,
|
inst_sfltsi_w,
|
inst_sfltu_w,
|
inst_sfltu_w,
|
inst_sfltui_w,
|
inst_sfltui_w,
|
inst_sfne_w,
|
inst_sfne_w,
|
inst_sfnei_w,
|
inst_sfnei_w,
|
inst_sys_w,
|
inst_sys_w,
|
inst_trap_w:
|
inst_trap_w:
|
invalid_inst_r = 1'b0;
|
invalid_inst_r = 1'b0;
|
default:
|
default:
|
invalid_inst_r = 1'b1;
|
invalid_inst_r = 1'b1;
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: ALU control
|
// Execute: ALU control
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_a <= 32'h00000000;
|
r_e_alu_a <= 32'h00000000;
|
r_e_alu_b <= 32'h00000000;
|
r_e_alu_b <= 32'h00000000;
|
r_e_rd <= 5'b00000;
|
r_e_rd <= 5'b00000;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
// Instruction not ready
|
// Instruction not ready
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
if (~execute_inst_r | stall_inst_r)
|
if (~execute_inst_r | stall_inst_r)
|
begin
|
begin
|
// Insert load result?
|
// Insert load result?
|
if (load_insert)
|
if (load_insert)
|
begin
|
begin
|
// Feed load result into pipeline
|
// Feed load result into pipeline
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_a <= load_result;
|
r_e_alu_a <= load_result;
|
r_e_alu_b <= 32'b0;
|
r_e_alu_b <= 32'b0;
|
r_e_rd <= r_load_rd;
|
r_e_rd <= r_load_rd;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// No ALU operation (output == input_a)
|
// No ALU operation (output == input_a)
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_func <= `ALU_NONE;
|
r_e_alu_a <= 32'b0;
|
r_e_alu_a <= 32'b0;
|
r_e_alu_b <= 32'b0;
|
r_e_alu_b <= 32'b0;
|
r_e_rd <= 5'b0;
|
r_e_rd <= 5'b0;
|
end
|
end
|
end
|
end
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
// Valid instruction
|
// Valid instruction
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
else if (~invalid_inst_r)
|
else if (~invalid_inst_r)
|
begin
|
begin
|
// Update ALU input flops
|
// Update ALU input flops
|
r_e_alu_func <= alu_func_r;
|
r_e_alu_func <= alu_func_r;
|
r_e_alu_a <= alu_input_a_r;
|
r_e_alu_a <= alu_input_a_r;
|
r_e_alu_b <= alu_input_b_r;
|
r_e_alu_b <= alu_input_b_r;
|
|
|
// Branch and link (Rd = LR/R9)
|
// Branch and link (Rd = LR/R9)
|
if (branch_link_r)
|
if (branch_link_r)
|
r_e_rd <= 5'd9;
|
r_e_rd <= 5'd9;
|
// Instruction with register writeback
|
// Instruction with register writeback
|
else if (write_rd_r)
|
else if (write_rd_r)
|
r_e_rd <= reg_rd_i;
|
r_e_rd <= reg_rd_i;
|
else
|
else
|
r_e_rd <= 5'b0;
|
r_e_rd <= 5'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: Update executed PC / opcode
|
// Execute: Update executed PC / opcode
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
r_e_opcode <= 32'h00000000;
|
r_e_opcode <= 32'h00000000;
|
r_e_opcode_pc <= 32'h00000000;
|
r_e_opcode_pc <= 32'h00000000;
|
|
|
r_stall <= 1'b0;
|
r_stall <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
r_stall <= stall_inst_r;
|
r_stall <= stall_inst_r;
|
|
|
// Instruction not ready
|
// Instruction not ready
|
if (~execute_inst_r | stall_inst_r)
|
if (~execute_inst_r | stall_inst_r)
|
begin
|
begin
|
// Store bubble opcode
|
// Store bubble opcode
|
r_e_opcode <= `OPCODE_INST_BUBBLE;
|
r_e_opcode <= `OPCODE_INST_BUBBLE;
|
r_e_opcode_pc <= opcode_pc_i;
|
r_e_opcode_pc <= opcode_pc_i;
|
end
|
end
|
// Valid instruction
|
// Valid instruction
|
else if (~invalid_inst_r)
|
else if (~invalid_inst_r)
|
begin
|
begin
|
// Store opcode
|
// Store opcode
|
r_e_opcode <= opcode_i;
|
r_e_opcode <= opcode_i;
|
r_e_opcode_pc <= opcode_pc_i;
|
r_e_opcode_pc <= opcode_pc_i;
|
|
|
`ifdef CONF_CORE_TRACE
|
`ifdef CONF_CORE_TRACE
|
$display("%08x: Execute 0x%08x", opcode_pc_i, opcode_i);
|
$display("%08x: Execute 0x%08x", opcode_pc_i, opcode_i);
|
$display(" rA[%d] = 0x%08x", reg_ra_i, reg_ra_r);
|
$display(" rA[%d] = 0x%08x", reg_ra_i, reg_ra_r);
|
$display(" rB[%d] = 0x%08x", reg_rb_i, reg_rb_r);
|
$display(" rB[%d] = 0x%08x", reg_rb_i, reg_rb_r);
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: Branch / exceptions
|
// Execute: Branch / exceptions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
r_pc_branch <= 32'h00000000;
|
r_pc_branch <= 32'h00000000;
|
r_pc_fetch <= 1'b0;
|
r_pc_fetch <= 1'b0;
|
|
|
// Status registers
|
// Status registers
|
r_epc <= 32'h00000000;
|
r_epc <= 32'h00000000;
|
r_sr <= 32'h00000000;
|
r_sr <= 32'h00000000;
|
r_esr <= 32'h00000000;
|
r_esr <= 32'h00000000;
|
|
|
fault_o <= 1'b0;
|
fault_o <= 1'b0;
|
|
|
r_nmi <= 1'b0;
|
r_nmi <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Record NMI in-case it can't be processed this cycle
|
// Record NMI in-case it can't be processed this cycle
|
if (nmi_i)
|
if (nmi_i)
|
r_nmi <= 1'b1;
|
r_nmi <= 1'b1;
|
|
|
// Reset branch request
|
// Reset branch request
|
r_pc_fetch <= 1'b0;
|
r_pc_fetch <= 1'b0;
|
|
|
// Update SR
|
// Update SR
|
r_sr <= next_sr_r;
|
r_sr <= next_sr_r;
|
|
|
// Instruction ready
|
// Instruction ready
|
if (execute_inst_r & ~stall_inst_r)
|
if (execute_inst_r & ~stall_inst_r)
|
begin
|
begin
|
// Exception: Instruction opcode not valid / supported, invalid PC
|
// Exception: Instruction opcode not valid / supported, invalid PC
|
if (invalid_inst_r || (opcode_pc_i[1:0] != 2'b00))
|
if (invalid_inst_r || (opcode_pc_i[1:0] != 2'b00))
|
begin
|
begin
|
// Save PC of next instruction
|
// Save PC of next instruction
|
r_epc <= next_pc_r;
|
r_epc <= next_pc_r;
|
r_esr <= next_sr_r;
|
r_esr <= next_sr_r;
|
|
|
// Disable further interrupts
|
// Disable further interrupts
|
r_sr <= 32'b0;
|
r_sr <= 32'b0;
|
|
|
// Set PC to exception vector
|
// Set PC to exception vector
|
if (invalid_inst_r)
|
if (invalid_inst_r)
|
r_pc_branch <= ISR_VECTOR + `VECTOR_ILLEGAL_INST;
|
r_pc_branch <= ISR_VECTOR + `VECTOR_ILLEGAL_INST;
|
else
|
else
|
r_pc_branch <= ISR_VECTOR + `VECTOR_BUS_ERROR;
|
r_pc_branch <= ISR_VECTOR + `VECTOR_BUS_ERROR;
|
r_pc_fetch <= 1'b1;
|
r_pc_fetch <= 1'b1;
|
|
|
fault_o <= 1'b1;
|
fault_o <= 1'b1;
|
end
|
end
|
// Exception: Syscall / Break
|
// Exception: Syscall / Break
|
else if (branch_except_r)
|
else if (branch_except_r)
|
begin
|
begin
|
// Save PC of next instruction
|
// Save PC of next instruction
|
r_epc <= next_pc_r;
|
r_epc <= next_pc_r;
|
r_esr <= next_sr_r;
|
r_esr <= next_sr_r;
|
|
|
// Disable further interrupts
|
// Disable further interrupts
|
r_sr <= 32'b0;
|
r_sr <= 32'b0;
|
|
|
// Set PC to exception vector
|
// Set PC to exception vector
|
r_pc_branch <= branch_target_r;
|
r_pc_branch <= branch_target_r;
|
r_pc_fetch <= 1'b1;
|
r_pc_fetch <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" Exception 0x%08x", branch_target_r);
|
$display(" Exception 0x%08x", branch_target_r);
|
`endif
|
`endif
|
end
|
end
|
// Non-maskable interrupt
|
// Non-maskable interrupt
|
else if (nmi_i | r_nmi)
|
else if (nmi_i | r_nmi)
|
begin
|
begin
|
r_nmi <= 1'b0;
|
r_nmi <= 1'b0;
|
|
|
// Save PC of next instruction
|
// Save PC of next instruction
|
if (branch_r)
|
if (branch_r)
|
r_epc <= branch_target_r;
|
r_epc <= branch_target_r;
|
// Next expected PC (current PC + 4)
|
// Next expected PC (current PC + 4)
|
else
|
else
|
r_epc <= next_pc_r;
|
r_epc <= next_pc_r;
|
|
|
r_esr <= next_sr_r;
|
r_esr <= next_sr_r;
|
|
|
// Disable further interrupts
|
// Disable further interrupts
|
r_sr <= 32'b0;
|
r_sr <= 32'b0;
|
|
|
// Set PC to exception vector
|
// Set PC to exception vector
|
r_pc_branch <= ISR_VECTOR + `VECTOR_NMI;
|
r_pc_branch <= ISR_VECTOR + `VECTOR_NMI;
|
r_pc_fetch <= 1'b1;
|
r_pc_fetch <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
|
$display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
|
`endif
|
`endif
|
end
|
end
|
// External interrupt
|
// External interrupt
|
else if (intr_i && next_sr_r[`OR32_SR_IEE])
|
else if (intr_i && next_sr_r[`OR32_SR_IEE])
|
begin
|
begin
|
// Save PC of next instruction & SR
|
// Save PC of next instruction & SR
|
if (branch_r)
|
if (branch_r)
|
r_epc <= branch_target_r;
|
r_epc <= branch_target_r;
|
// Next expected PC (current PC + 4)
|
// Next expected PC (current PC + 4)
|
else
|
else
|
r_epc <= next_pc_r;
|
r_epc <= next_pc_r;
|
|
|
r_esr <= next_sr_r;
|
r_esr <= next_sr_r;
|
|
|
// Disable further interrupts
|
// Disable further interrupts
|
r_sr <= 32'b0;
|
r_sr <= 32'b0;
|
|
|
// Set PC to external interrupt vector
|
// Set PC to external interrupt vector
|
r_pc_branch <= ISR_VECTOR + `VECTOR_EXTINT;
|
r_pc_branch <= ISR_VECTOR + `VECTOR_EXTINT;
|
r_pc_fetch <= 1'b1;
|
r_pc_fetch <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" External Interrupt 0x%08x", ISR_VECTOR + `VECTOR_EXTINT);
|
$display(" External Interrupt 0x%08x", ISR_VECTOR + `VECTOR_EXTINT);
|
`endif
|
`endif
|
end
|
end
|
// Branch (l.bf, l.bnf, l.j, l.jal, l.jr, l.jalr, l.rfe)
|
// Branch (l.bf, l.bnf, l.j, l.jal, l.jr, l.jalr, l.rfe)
|
else if (branch_r)
|
else if (branch_r)
|
begin
|
begin
|
// Perform branch
|
// Perform branch
|
r_pc_branch <= branch_target_r;
|
r_pc_branch <= branch_target_r;
|
r_pc_fetch <= 1'b1;
|
r_pc_fetch <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" Branch to 0x%08x", branch_target_r);
|
$display(" Branch to 0x%08x", branch_target_r);
|
`endif
|
`endif
|
end
|
end
|
// Non branch
|
// Non branch
|
else
|
else
|
begin
|
begin
|
// Update EPC / ESR which may have been updated
|
// Update EPC / ESR which may have been updated
|
// by an MTSPR write
|
// by an MTSPR write
|
r_epc <= next_epc_r;
|
r_epc <= next_epc_r;
|
r_esr <= next_esr_r;
|
r_esr <= next_esr_r;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: Memory operations
|
// Execute: Memory operations
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
// Data memory
|
// Data memory
|
dmem_addr_o <= 32'h00000000;
|
dmem_addr_o <= 32'h00000000;
|
dmem_data_out_o <= 32'h00000000;
|
dmem_data_out_o <= 32'h00000000;
|
dmem_rd_o <= 1'b0;
|
dmem_we_o <= 1'b0;
|
dmem_wr_o <= 4'b0000;
|
dmem_sel_o <= 4'b0000;
|
|
dmem_stb_o <= 1'b0;
|
|
dmem_cyc_o <= 1'b0;
|
|
|
r_mem_load <= 1'b0;
|
r_mem_load <= 1'b0;
|
r_mem_store <= 1'b0;
|
r_mem_store <= 1'b0;
|
r_mem_access <= 1'b0;
|
r_mem_access <= 1'b0;
|
|
|
r_load_rd <= 5'b00000;
|
r_load_rd <= 5'b00000;
|
r_load_inst <= 8'h00;
|
r_load_inst <= 8'h00;
|
r_load_offset <= 2'b00;
|
r_load_offset <= 2'b00;
|
|
|
d_mem_load <= 1'b0;
|
d_mem_load <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
// If memory access accepted by slave
|
// If memory access accepted by slave
|
if (dmem_accept_i)
|
if (~dmem_stall_i)
|
begin
|
dmem_stb_o <= 1'b0;
|
dmem_rd_o <= 1'b0;
|
|
dmem_wr_o <= 4'b0000;
|
|
end
|
|
|
|
|
if (dmem_ack_i)
|
|
dmem_cyc_o <= 1'b0;
|
r_mem_access <= 1'b0;
|
r_mem_access <= 1'b0;
|
d_mem_load <= r_mem_access & r_mem_load;
|
d_mem_load <= r_mem_access & r_mem_load;
|
|
|
// Pending accesses
|
// Pending accesses
|
r_mem_load <= load_pending;
|
r_mem_load <= load_pending;
|
r_mem_store <= store_pending;
|
r_mem_store <= store_pending;
|
|
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
// Valid instruction
|
// Valid instruction
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
begin
|
begin
|
// Branch and link (Rd = LR/R9)
|
// Branch and link (Rd = LR/R9)
|
if (branch_link_r)
|
if (branch_link_r)
|
begin
|
begin
|
// Load outstanding, check if result target is being
|
// Load outstanding, check if result target is being
|
// overwritten (to avoid WAR hazard)
|
// overwritten (to avoid WAR hazard)
|
if (r_load_rd == 5'd9)
|
if (r_load_rd == 5'd9)
|
// Ditch load result when it arrives
|
// Ditch load result when it arrives
|
r_load_rd <= 5'b00000;
|
r_load_rd <= 5'b00000;
|
end
|
end
|
// Instruction with register writeback
|
// Instruction with register writeback
|
else if (write_rd_r)
|
else if (write_rd_r)
|
begin
|
begin
|
// Load outstanding, check if result target is being
|
// Load outstanding, check if result target is being
|
// overwritten (to avoid WAR hazard)
|
// overwritten (to avoid WAR hazard)
|
if (reg_rd_i == r_load_rd && ~load_inst_r)
|
if (reg_rd_i == r_load_rd && ~load_inst_r)
|
// Ditch load result when it arrives
|
// Ditch load result when it arrives
|
r_load_rd <= 5'b00000;
|
r_load_rd <= 5'b00000;
|
end
|
end
|
|
|
case (1'b1)
|
case (1'b1)
|
|
|
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
|
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
|
load_inst_r:
|
load_inst_r:
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
|
dmem_data_out_o <= 32'h00000000;
|
dmem_data_out_o <= 32'h00000000;
|
dmem_rd_o <= 1'b1;
|
dmem_sel_o <= 4'b1111;
|
|
dmem_we_o <= 1'b0;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
|
|
// Mark load as pending
|
// Mark load as pending
|
r_mem_load <= 1'b1;
|
r_mem_load <= 1'b1;
|
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
|
|
// Record target register
|
// Record target register
|
r_load_rd <= reg_rd_i;
|
r_load_rd <= reg_rd_i;
|
r_load_inst <= inst_r;
|
r_load_inst <= inst_r;
|
r_load_offset <= mem_addr_r[1:0];
|
r_load_offset <= mem_addr_r[1:0];
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" Load from 0x%08x to R%d", mem_addr_r, reg_rd_i);
|
$display(" Load from 0x%08x to R%d", mem_addr_r, reg_rd_i);
|
`endif
|
`endif
|
end
|
end
|
|
|
inst_sb_w: // l.sb
|
inst_sb_w: // l.sb
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
|
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
case (mem_addr_r[1:0])
|
case (mem_addr_r[1:0])
|
2'b00 :
|
2'b00 :
|
begin
|
begin
|
dmem_data_out_o <= {reg_rb_r[7:0],24'h000000};
|
dmem_data_out_o <= {reg_rb_r[7:0],24'h000000};
|
dmem_wr_o <= 4'b1000;
|
dmem_sel_o <= 4'b1000;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b01 :
|
2'b01 :
|
begin
|
begin
|
dmem_data_out_o <= {{8'h00,reg_rb_r[7:0]},16'h0000};
|
dmem_data_out_o <= {{8'h00,reg_rb_r[7:0]},16'h0000};
|
dmem_wr_o <= 4'b0100;
|
dmem_sel_o <= 4'b0100;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b10 :
|
2'b10 :
|
begin
|
begin
|
dmem_data_out_o <= {{16'h0000,reg_rb_r[7:0]},8'h00};
|
dmem_data_out_o <= {{16'h0000,reg_rb_r[7:0]},8'h00};
|
dmem_wr_o <= 4'b0010;
|
dmem_sel_o <= 4'b0010;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
dmem_data_out_o <= {24'h000000,reg_rb_r[7:0]};
|
dmem_data_out_o <= {24'h000000,reg_rb_r[7:0]};
|
dmem_wr_o <= 4'b0001;
|
dmem_sel_o <= 4'b0001;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
default :
|
default :
|
begin
|
;
|
dmem_data_out_o <= 32'h00000000;
|
|
dmem_wr_o <= 4'b0000;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_sh_w: // l.sh
|
inst_sh_w: // l.sh
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
|
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
case (mem_addr_r[1:0])
|
case (mem_addr_r[1:0])
|
2'b00 :
|
2'b00 :
|
begin
|
begin
|
dmem_data_out_o <= {reg_rb_r[15:0],16'h0000};
|
dmem_data_out_o <= {reg_rb_r[15:0],16'h0000};
|
dmem_wr_o <= 4'b1100;
|
dmem_sel_o <= 4'b1100;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b10 :
|
2'b10 :
|
begin
|
begin
|
dmem_data_out_o <= {16'h0000,reg_rb_r[15:0]};
|
dmem_data_out_o <= {16'h0000,reg_rb_r[15:0]};
|
dmem_wr_o <= 4'b0011;
|
dmem_sel_o <= 4'b0011;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
default :
|
default :
|
begin
|
;
|
dmem_data_out_o <= 32'h00000000;
|
|
dmem_wr_o <= 4'b0000;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_sw_w: // l.sw
|
inst_sw_w: // l.sw
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
|
dmem_data_out_o <= reg_rb_r;
|
dmem_data_out_o <= reg_rb_r;
|
dmem_wr_o <= 4'b1111;
|
dmem_sel_o <= 4'b1111;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" Store R%d to 0x%08x = 0x%08x", reg_rb_i, {mem_addr_r[31:2],2'b00}, reg_rb_r);
|
$display(" Store R%d to 0x%08x = 0x%08x", reg_rb_i, {mem_addr_r[31:2],2'b00}, reg_rb_r);
|
`endif
|
`endif
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: Misc operations
|
// Execute: Misc operations
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
break_o <= 1'b0;
|
break_o <= 1'b0;
|
icache_flush_o <= 1'b0;
|
icache_flush_o <= 1'b0;
|
dcache_flush_o <= 1'b0;
|
dcache_flush_o <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
break_o <= 1'b0;
|
break_o <= 1'b0;
|
icache_flush_o <= 1'b0;
|
icache_flush_o <= 1'b0;
|
dcache_flush_o <= 1'b0;
|
dcache_flush_o <= 1'b0;
|
|
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
// Valid instruction
|
// Valid instruction
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
begin
|
begin
|
case (1'b1)
|
case (1'b1)
|
inst_mtspr_w: // l.mtspr
|
inst_mtspr_w: // l.mtspr
|
begin
|
begin
|
case (mxspr_uint16_r)
|
case (mxspr_uint16_r)
|
// SR - Supervision register
|
// SR - Supervision register
|
`SPR_REG_SR:
|
`SPR_REG_SR:
|
begin
|
begin
|
// Cache flush request?
|
// Cache flush request?
|
icache_flush_o <= reg_rb_r[`OR32_SR_ICACHE_FLUSH];
|
icache_flush_o <= reg_rb_r[`OR32_SR_ICACHE_FLUSH];
|
dcache_flush_o <= reg_rb_r[`OR32_SR_DCACHE_FLUSH];
|
dcache_flush_o <= reg_rb_r[`OR32_SR_DCACHE_FLUSH];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_trap_w: // l.trap
|
inst_trap_w: // l.trap
|
break_o <= 1'b1;
|
break_o <= 1'b1;
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Execute: NOP (simulation) operations
|
// Execute: NOP (simulation) operations
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`ifdef SIMULATION
|
`ifdef SIMULATION
|
always @ (posedge clk_i or posedge rst_i)
|
always @ (posedge clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
`ifdef SIM_EXT_PUTC
|
`ifdef SIM_EXT_PUTC
|
r_putc <= 8'b0;
|
r_putc <= 8'b0;
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
`ifdef SIM_EXT_PUTC
|
`ifdef SIM_EXT_PUTC
|
r_putc <= 8'b0;
|
r_putc <= 8'b0;
|
`endif
|
`endif
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
// Valid instruction
|
// Valid instruction
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
if (execute_inst_r & ~stall_inst_r & ~invalid_inst_r)
|
begin
|
begin
|
|
|
case (1'b1)
|
case (1'b1)
|
inst_nop_w: // l.nop
|
inst_nop_w: // l.nop
|
begin
|
begin
|
case (uint16_r)
|
case (uint16_r)
|
// NOP_PUTC
|
// NOP_PUTC
|
16'h0004:
|
16'h0004:
|
begin
|
begin
|
`ifdef SIM_EXT_PUTC
|
`ifdef SIM_EXT_PUTC
|
r_putc <= reg_ra_r[7:0];
|
r_putc <= reg_ra_r[7:0];
|
`else
|
`else
|
$write("%c", reg_ra_r[7:0]);
|
$write("%c", reg_ra_r[7:0]);
|
`endif
|
`endif
|
end
|
end
|
// NOP
|
// NOP
|
16'h0000: ;
|
16'h0000: ;
|
endcase
|
endcase
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
// Assignments
|
// Assignments
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
|
|
assign branch_pc_o = r_pc_branch;
|
assign branch_pc_o = r_pc_branch;
|
assign branch_o = r_pc_fetch;
|
assign branch_o = r_pc_fetch;
|
assign stall_o = r_stall;
|
assign stall_o = r_stall;
|
|
|
assign opcode_o = r_e_opcode;
|
assign opcode_o = r_e_opcode;
|
|
|
assign reg_rd_o = r_e_rd;
|
assign reg_rd_o = r_e_rd;
|
assign reg_rd_value_o = r_e_result;
|
assign reg_rd_value_o = r_e_result;
|
|
|
assign mult_o = 1'b0;
|
assign mult_o = 1'b0;
|
assign mult_res_o = 32'b0;
|
assign mult_res_o = 32'b0;
|
|
|
`include "altor32_funcs.v"
|
`include "altor32_funcs.v"
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
// Hooks for debug
|
// Hooks for debug
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
`ifdef verilator
|
`ifdef verilator
|
function [31:0] get_opcode_ex;
|
function [31:0] get_opcode_ex;
|
// verilator public
|
// verilator public
|
get_opcode_ex = r_e_opcode;
|
get_opcode_ex = r_e_opcode;
|
endfunction
|
endfunction
|
function [31:0] get_pc_ex;
|
function [31:0] get_pc_ex;
|
// verilator public
|
// verilator public
|
get_pc_ex = r_e_opcode_pc;
|
get_pc_ex = r_e_opcode_pc;
|
endfunction
|
endfunction
|
function [7:0] get_putc;
|
function [7:0] get_putc;
|
// verilator public
|
// verilator public
|
`ifdef SIM_EXT_PUTC
|
`ifdef SIM_EXT_PUTC
|
get_putc = r_putc;
|
get_putc = r_putc;
|
`else
|
`else
|
get_putc = 8'b0;
|
get_putc = 8'b0;
|
`endif
|
`endif
|
endfunction
|
endfunction
|
|
function [0:0] get_reg_valid;
|
|
// verilator public
|
|
get_reg_valid = ~(resolve_failed | load_stall);
|
|
endfunction
|
|
function [4:0] get_reg_ra;
|
|
// verilator public
|
|
get_reg_ra = reg_ra_i;
|
|
endfunction
|
|
function [31:0] get_reg_ra_value;
|
|
// verilator public
|
|
get_reg_ra_value = ra_value_resolved;
|
|
endfunction
|
|
function [4:0] get_reg_rb;
|
|
// verilator public
|
|
get_reg_rb = reg_rb_i;
|
|
endfunction
|
|
function [31:0] get_reg_rb_value;
|
|
// verilator public
|
|
get_reg_rb_value = rb_value_resolved;
|
|
endfunction
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|