| Line 68... |
Line 68... |
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
// Params
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
parameter BOOT_VECTOR = 32'h00000000;
|
parameter BOOT_VECTOR = 32'h00000000;
|
|
|
|
// Option: Number of ways (supports 1 or 2)
|
|
parameter CACHE_NUM_WAYS = 1;
|
|
|
|
// Option: Number of cache lines (2^param) * line_size_bytes = cache size
|
|
parameter CACHE_LINE_ADDR_WIDTH = 8 - (CACHE_NUM_WAYS-1); /* 256 lines total across all ways */
|
|
|
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
|
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
|
parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 4 words per line */
|
parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 8 words per line */
|
parameter CACHE_LINE_ADDR_WIDTH = 8; /* 256 lines */
|
|
parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 111 */
|
parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 128 tag entries */
|
parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */
|
parameter CACHE_DSIZE = CACHE_NUM_WAYS * (2 ** CACHE_LINE_ADDR_WIDTH) * CACHE_LINE_SIZE_BYTES; /* 8KB data */
|
parameter CACHE_DSIZE = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */
|
|
parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 10-bits */
|
parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 10-bits */
|
|
|
parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */
|
parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */
|
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 1; /* 15 bits of data (tag entry size minus valid bit) */
|
parameter CACHE_TAG_STAT_BITS = 1 + (CACHE_NUM_WAYS-1);
|
|
|
|
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - CACHE_TAG_STAT_BITS; /* 15 bits of data (tag entry size minus valid / LRU bit) */
|
|
|
parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
|
parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
|
parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
|
parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
|
|
|
// Tag fields
|
// Tag fields
|
parameter CACHE_TAG_VALID_BIT = 15;
|
parameter CACHE_TAG_VALID_BIT = 15;
|
|
parameter CACHE_TAG_LRU_BIT = 14; // If CACHE_NUM_WAYS > 1
|
|
parameter CACHE_TAG_ADDR_BITS = CACHE_TAG_WIDTH - CACHE_TAG_STAT_BITS;
|
|
|
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
|
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
|
// |--------------| | | | | | | | | | | | | | | | |
|
// |--------------| | | | | | | | | | | | | | | | |
|
// +--------------------+ +-------------------+ +-----------+
|
// +-----------------+ +-------------------+ +-----------+
|
// Tag entry Line address Address
|
// Tag entry Line address Address
|
// (15-bits) (8-bits) within line
|
// (14/15-bits) (7/8-bits) within line
|
// (5-bits)
|
// (5-bits)
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Registers / Wires
|
// Registers / Wires
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// Tag read / write data
|
// Tag read / write data
|
wire [CACHE_TAG_WIDTH-1:0] tag_out_w;
|
|
reg [CACHE_TAG_WIDTH-1:0] tag_in_r;
|
|
reg tag_wr_r;
|
reg tag_wr_r;
|
|
wire [CACHE_TAG_WIDTH-1:0] tag_out0_w;
|
|
reg [CACHE_TAG_WIDTH-1:0] tag_in0_r;
|
|
wire [CACHE_TAG_WIDTH-1:0] tag_out1_w;
|
|
reg [CACHE_TAG_WIDTH-1:0] tag_in1_r;
|
|
|
// Tag address
|
// Tag address
|
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_w;
|
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_w;
|
|
|
// Data memory read / write
|
// Data memory read / write
|
wire [CACHE_DWIDTH-1:0] address_rd_w;
|
wire [CACHE_DWIDTH-1:0] address_rd_w;
|
wire [CACHE_DWIDTH-1:0] address_wr_w;
|
wire [CACHE_DWIDTH-1:0] address_wr_w;
|
wire cache_wr_w;
|
|
|
wire cache_wr0_w;
|
|
wire cache_wr1_w;
|
|
|
|
reg way_update_q;
|
|
|
// Current / Miss PC
|
// Current / Miss PC
|
reg [31:0] last_pc_q;
|
reg [31:0] last_pc_q;
|
reg [31:0] miss_pc_q;
|
reg [31:0] miss_pc_q;
|
|
|
| Line 137... |
Line 152... |
|
|
// Cache read address
|
// Cache read address
|
assign address_rd_w = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
|
assign address_rd_w = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
|
|
|
// Cache miss output if requested PC is not in the tag memory
|
// Cache miss output if requested PC is not in the tag memory
|
wire miss_w = ~tag_out_w[CACHE_TAG_VALID_BIT] |
|
wire miss0_w = ~tag_out0_w[CACHE_TAG_VALID_BIT] |
|
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out_w[14:0]);
|
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out0_w[CACHE_TAG_ADDR_BITS-1:0]);
|
|
|
|
wire miss1_w = ~tag_out1_w[CACHE_TAG_VALID_BIT] |
|
|
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out1_w[CACHE_TAG_ADDR_BITS-1:0]);
|
|
|
// Stall the CPU if cache state machine is not idle!
|
// Stall the CPU if cache state machine is not idle!
|
wire busy_w = (state_q != STATE_CHECK) | read_while_busy_q;
|
wire busy_w = (state_q != STATE_CHECK) | read_while_busy_q;
|
|
|
// Cache output valid
|
// Cache output valid
|
assign valid_o = busy_w ? 1'b0 : ~miss_w;
|
assign valid_o = busy_w ? 1'b0 : ~(miss0_w & miss1_w);
|
|
|
// Flushing: Last line to flush
|
// Flushing: Last line to flush
|
wire flush_last_w = (flush_addr_q == {CACHE_LINE_ADDR_WIDTH{1'b0}});
|
wire flush_last_w = (flush_addr_q == {CACHE_LINE_ADDR_WIDTH{1'b0}});
|
|
|
// Is this a cache miss?
|
// Is this a cache miss?
|
wire cache_miss_w = miss_w & // Tag lookup failed
|
wire cache_miss_w = miss0_w & miss1_w & // Tag lookup failed
|
!rd_i & // NOT new read request cycle
|
!rd_i & // NOT new read request cycle
|
!read_while_busy_q & // NOT pending read whilst busy
|
!read_while_busy_q & // NOT pending read whilst busy
|
!flush_q & // NOT flush request
|
!flush_q & // NOT flush request
|
!invalidate_i;
|
!invalidate_i;
|
|
|
| Line 226... |
Line 244... |
else
|
else
|
state_q <= next_state_r;
|
state_q <= next_state_r;
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
// Select way to be replaced
|
|
//-----------------------------------------------------------------
|
|
reg lru_way_r;
|
|
|
|
// 2-Way
|
|
generate
|
|
if (CACHE_NUM_WAYS >= 2)
|
|
begin: LRU_SELECT
|
|
always @ *
|
|
begin
|
|
if (tag_out0_w[CACHE_TAG_LRU_BIT])
|
|
lru_way_r = 1'b0;
|
|
else
|
|
lru_way_r = 1'b1;
|
|
end
|
|
end
|
|
// 1-Way
|
|
else
|
|
begin: LRU_FIXED
|
|
wire lru_way_w = 1'b0;
|
|
always @ *
|
|
lru_way_r = lru_way_w;
|
|
end
|
|
endgenerate
|
|
|
|
//-----------------------------------------------------------------
|
// Flop request details
|
// Flop request details
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
reg [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_q;
|
|
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
miss_pc_q <= BOOT_VECTOR + `VECTOR_RESET;
|
miss_pc_q <= BOOT_VECTOR + `VECTOR_RESET;
|
last_pc_q <= 32'h00000000;
|
last_pc_q <= 32'h00000000;
|
|
|
|
tag_address_q <= {CACHE_LINE_ADDR_WIDTH{1'b0}};
|
|
way_update_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
last_pc_q <= pc_i;
|
last_pc_q <= pc_i;
|
|
tag_address_q <= tag_address_w;
|
|
|
case (state_q)
|
case (state_q)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache hit (or new read request), store fetch PC
|
// Cache hit (or new read request), store fetch PC
|
if (!cache_miss_w)
|
if (!cache_miss_w)
|
|
begin
|
miss_pc_q <= pc_i;
|
miss_pc_q <= pc_i;
|
end
|
end
|
|
// Cache miss
|
|
else
|
|
begin
|
|
// Select line way to replace
|
|
way_update_q <= lru_way_r;
|
|
end
|
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
| Line 293... |
Line 351... |
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Cache Tag Write
|
// Cache Tag Write
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ *
|
always @ *
|
begin
|
begin
|
tag_in_r = {CACHE_TAG_WIDTH{1'b0}};
|
tag_in0_r = tag_out0_w;
|
|
tag_in1_r = tag_out1_w;
|
tag_wr_r = 1'b0;
|
tag_wr_r = 1'b0;
|
|
|
case (state_q)
|
case (state_q)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
| Line 307... |
Line 366... |
begin
|
begin
|
// Cache miss (& new read request not pending)
|
// Cache miss (& new read request not pending)
|
if (cache_miss_w)
|
if (cache_miss_w)
|
begin
|
begin
|
// Update tag memory with this line's details
|
// Update tag memory with this line's details
|
tag_in_r = {1'b1, miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
|
if (lru_way_r)
|
|
begin
|
|
tag_in1_r[CACHE_TAG_ADDR_BITS-1:0] = miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW];
|
|
tag_in1_r[CACHE_TAG_VALID_BIT] = 1'b1;
|
|
|
|
if (CACHE_NUM_WAYS >= 2)
|
|
begin
|
|
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b0;
|
|
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
tag_in0_r[CACHE_TAG_ADDR_BITS-1:0] = miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW];
|
|
tag_in0_r[CACHE_TAG_VALID_BIT] = 1'b1;
|
|
|
|
if (CACHE_NUM_WAYS >= 2)
|
|
begin
|
|
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b0;
|
|
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b1;
|
|
end
|
|
end
|
|
|
|
tag_wr_r = 1'b1;
|
|
end
|
|
// Update LRU (if possible)
|
|
else if ((tag_address_q == tag_address_w) && (CACHE_NUM_WAYS >= 2))
|
|
begin
|
|
// Hit Way 0
|
|
if (!miss0_w)
|
|
begin
|
|
// Least recently used way is 1
|
|
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b1;
|
|
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b0;
|
|
end
|
|
// Hit Way 1
|
|
else
|
|
begin
|
|
// Least recently used way is 0
|
|
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b1;
|
|
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b0;
|
|
end
|
|
|
tag_wr_r = 1'b1;
|
tag_wr_r = 1'b1;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
;
|
;
|
| Line 413... |
Line 514... |
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Tag memory
|
// Tag memory
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
wire [(CACHE_NUM_WAYS*CACHE_TAG_WIDTH)-1:0] tag_in;
|
|
wire [(CACHE_NUM_WAYS*CACHE_TAG_WIDTH)-1:0] tag_out;
|
|
|
altor32_ram_dp
|
altor32_ram_dp
|
#(
|
#(
|
.WIDTH(CACHE_TAG_WIDTH),
|
.WIDTH(CACHE_TAG_WIDTH * CACHE_NUM_WAYS),
|
.SIZE(CACHE_LINE_ADDR_WIDTH)
|
.SIZE(CACHE_LINE_ADDR_WIDTH)
|
)
|
)
|
u1_tag_mem
|
u_tag_mem
|
(
|
(
|
// Tag read/write port
|
// Tag read/write port
|
.aclk_i(clk_i),
|
.aclk_i(clk_i),
|
.adat_o(tag_out_w),
|
.adat_o(tag_out),
|
.adat_i(tag_in_r),
|
.adat_i(tag_in),
|
.aadr_i(tag_address_w),
|
.aadr_i(tag_address_w),
|
.awr_i(tag_wr_r),
|
.awr_i(tag_wr_r),
|
|
|
// Tag invalidate port
|
// Tag invalidate port
|
.bclk_i(clk_i),
|
.bclk_i(clk_i),
|
.badr_i(flush_addr_q),
|
.badr_i(flush_addr_q),
|
.bdat_o(/*open*/),
|
.bdat_o(/*open*/),
|
.bdat_i({CACHE_TAG_WIDTH{1'b0}}),
|
.bdat_i({(CACHE_NUM_WAYS*CACHE_TAG_WIDTH){1'b0}}),
|
.bwr_i(flush_wr_q)
|
.bwr_i(flush_wr_q)
|
);
|
);
|
|
|
|
// 2-Way
|
|
generate
|
|
if (CACHE_NUM_WAYS >= 2)
|
|
begin: TAG_2WAY
|
|
assign tag_in = {tag_in1_r, tag_in0_r};
|
|
assign {tag_out1_w, tag_out0_w} = tag_out;
|
|
end
|
|
// 1-Way
|
|
else
|
|
begin: TAG_1WAY
|
|
assign tag_in = tag_in0_r;
|
|
assign tag_out0_w = tag_out;
|
|
assign tag_out1_w = {(CACHE_TAG_WIDTH){1'b0}};
|
|
end
|
|
endgenerate
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Data memory
|
// Data memory
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
wire [31:0] way0_instruction_w /*verilator public*/;
|
|
wire [31:0] way1_instruction_w /*verilator public*/;
|
|
|
|
// Way 0 Instruction Memory
|
altor32_ram_dp
|
altor32_ram_dp
|
#(
|
#(
|
.WIDTH(32),
|
.WIDTH(32),
|
.SIZE(CACHE_DWIDTH)
|
.SIZE(CACHE_DWIDTH)
|
)
|
)
|
u2_data_mem
|
u2_data_way0
|
(
|
(
|
// Data read port
|
// Data read port
|
.aclk_i(clk_i),
|
.aclk_i(clk_i),
|
.aadr_i(address_rd_w),
|
.aadr_i(address_rd_w),
|
.adat_o(instruction_o),
|
.adat_o(way0_instruction_w),
|
.adat_i(32'h00),
|
.adat_i(32'h00),
|
.awr_i(1'b0),
|
.awr_i(1'b0),
|
|
|
// Data write port
|
// Data write port
|
.bclk_i(clk_i),
|
.bclk_i(clk_i),
|
.badr_i(address_wr_w),
|
.badr_i(address_wr_w),
|
.bdat_o(/*open*/),
|
.bdat_o(/*open*/),
|
.bdat_i(mem_data_w),
|
.bdat_i(mem_data_w),
|
.bwr_i(cache_wr_w)
|
.bwr_i(cache_wr0_w)
|
);
|
);
|
|
|
|
// Way 1 Instruction Memory
|
|
altor32_ram_dp
|
|
#(
|
|
.WIDTH(32),
|
|
.SIZE(CACHE_DWIDTH)
|
|
)
|
|
u2_data_way1
|
|
(
|
|
// Data read port
|
|
.aclk_i(clk_i),
|
|
.aadr_i(address_rd_w),
|
|
.adat_o(way1_instruction_w),
|
|
.adat_i(32'h00),
|
|
.awr_i(1'b0),
|
|
|
|
// Data write port
|
|
.bclk_i(clk_i),
|
|
.badr_i(address_wr_w),
|
|
.bdat_o(/*open*/),
|
|
.bdat_i(mem_data_w),
|
|
.bwr_i(cache_wr1_w)
|
|
);
|
|
|
|
// Select between ways for result
|
|
assign instruction_o = (miss0_w == 1'b0) ? way0_instruction_w : way1_instruction_w;
|
|
|
// Write to cache on wishbone response
|
// Write to cache on wishbone response
|
assign address_wr_w = {miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH], mem_resp_addr_w[CACHE_LINE_SIZE_WIDTH-1:2]};
|
assign address_wr_w = {miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH], mem_resp_addr_w[CACHE_LINE_SIZE_WIDTH-1:2]};
|
|
|
assign cache_wr_w = (state_q == STATE_FETCH) & mem_valid_w;
|
assign cache_wr0_w = (state_q == STATE_FETCH) & mem_valid_w & ~way_update_q;
|
|
assign cache_wr1_w = (state_q == STATE_FETCH) & mem_valid_w & way_update_q;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
