//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// AltOR32
|
// AltOR32
|
// Alternative Lightweight OpenRisc
|
// Alternative Lightweight OpenRisc
|
// V2.1
|
// V2.1
|
// Ultra-Embedded.com
|
// Ultra-Embedded.com
|
// Copyright 2011 - 2014
|
// Copyright 2011 - 2014
|
//
|
//
|
// Email: admin@ultra-embedded.com
|
// Email: admin@ultra-embedded.com
|
//
|
//
|
// License: LGPL
|
// License: LGPL
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//
|
//
|
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
|
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
|
//
|
//
|
// This source file is free software; you can redistribute it
|
// This source file is free software; you can redistribute it
|
// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
// Public License as published by the Free Software Foundation;
|
// Public License as published by the Free Software Foundation;
|
// either version 2.1 of the License, or (at your option) any
|
// either version 2.1 of the License, or (at your option) any
|
// later version.
|
// later version.
|
//
|
//
|
// This source is distributed in the hope that it will be
|
// This source is distributed in the hope that it will be
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// PURPOSE. See the GNU Lesser General Public License for more
|
// details.
|
// details.
|
//
|
//
|
// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, write to the
|
// Public License along with this source; if not, write to the
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
|
// Boston, MA 02111-1307 USA
|
// Boston, MA 02111-1307 USA
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Includes
|
// Includes
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`include "altor32_defs.v"
|
`include "altor32_defs.v"
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Module - Instruction Cache
|
// Module - Instruction Cache
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
module altor32_icache
|
module altor32_icache
|
(
|
(
|
input clk_i /*verilator public*/,
|
input clk_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
input rst_i /*verilator public*/,
|
|
|
// Processor interface
|
// Processor interface
|
input rd_i /*verilator public*/,
|
input rd_i /*verilator public*/,
|
input [31:0] pc_i /*verilator public*/,
|
input [31:0] pc_i /*verilator public*/,
|
output [31:0] instruction_o /*verilator public*/,
|
output [31:0] instruction_o /*verilator public*/,
|
output valid_o /*verilator public*/,
|
output valid_o /*verilator public*/,
|
input invalidate_i /*verilator public*/,
|
input invalidate_i /*verilator public*/,
|
|
|
// Memory interface
|
// Memory interface
|
output reg [31:0] wbm_addr_o /*verilator public*/,
|
output [31:0] wbm_addr_o /*verilator public*/,
|
input [31:0] wbm_dat_i /*verilator public*/,
|
input [31:0] wbm_dat_i /*verilator public*/,
|
output reg [2:0] wbm_cti_o /*verilator public*/,
|
output [2:0] wbm_cti_o /*verilator public*/,
|
output reg wbm_cyc_o /*verilator public*/,
|
output wbm_cyc_o /*verilator public*/,
|
output reg wbm_stb_o /*verilator public*/,
|
output wbm_stb_o /*verilator public*/,
|
input wbm_stall_i/*verilator public*/,
|
input wbm_stall_i/*verilator public*/,
|
input wbm_ack_i/*verilator public*/
|
input wbm_ack_i/*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
// Params
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
parameter BOOT_VECTOR = 32'h00000000;
|
parameter BOOT_VECTOR = 32'h00000000;
|
|
|
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
|
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
|
parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 4 words per line */
|
parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 4 words per line */
|
parameter CACHE_LINE_ADDR_WIDTH = 8; /* 256 lines */
|
parameter CACHE_LINE_ADDR_WIDTH = 8; /* 256 lines */
|
parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 111 */
|
parameter CACHE_LINE_WORDS_IDX_MAX = CACHE_LINE_SIZE_WIDTH - 2; /* 3-bit = 111 */
|
parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */
|
parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 256 tag entries */
|
parameter CACHE_DSIZE = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */
|
parameter CACHE_DSIZE = CACHE_LINE_ADDR_WIDTH * CACHE_LINE_SIZE_BYTES; /* 8KB data */
|
parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 10-bits */
|
parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 10-bits */
|
|
|
parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */
|
parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */
|
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 1; /* 15 bits of data (tag entry size minus valid bit) */
|
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - 1; /* 15 bits of data (tag entry size minus valid bit) */
|
|
|
parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
|
parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
|
parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
|
parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
|
|
|
// Tag fields
|
// Tag fields
|
parameter CACHE_TAG_VALID_BIT = 15;
|
parameter CACHE_TAG_VALID_BIT = 15;
|
|
|
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
|
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
|
// |--------------| | | | | | | | | | | | | | | | |
|
// |--------------| | | | | | | | | | | | | | | | |
|
// +--------------------+ +-------------------+ +-----------+
|
// +--------------------+ +-------------------+ +-----------+
|
// Tag entry Line address Address
|
// Tag entry Line address Address
|
// (15-bits) (8-bits) within line
|
// (15-bits) (8-bits) within line
|
// (5-bits)
|
// (5-bits)
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Registers / Wires
|
// Registers / Wires
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
// Tag read / write data
|
// Tag read / write data
|
wire [CACHE_TAG_WIDTH-1:0] tag_data_out;
|
wire [CACHE_TAG_WIDTH-1:0] tag_out_w;
|
reg [CACHE_TAG_WIDTH-1:0] tag_data_in;
|
reg [CACHE_TAG_WIDTH-1:0] tag_in_r;
|
reg tag_wr;
|
reg tag_wr_r;
|
|
|
// Tag address
|
// Tag address
|
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_entry;
|
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_w;
|
|
|
// Data memory read / write
|
// Data memory read / write
|
wire [CACHE_DWIDTH-1:0] cache_address_rd;
|
wire [CACHE_DWIDTH-1:0] address_rd_w;
|
wire [CACHE_DWIDTH-1:0] cache_address_wr;
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wire [CACHE_DWIDTH-1:0] address_wr_w;
|
reg [31:0] cache_data_in;
|
wire cache_wr_w;
|
wire cache_wr;
|
|
|
|
// Word currently being fetched within a line
|
|
reg [CACHE_LINE_SIZE_WIDTH-3:0] mem_fetch_word;
|
|
reg [CACHE_LINE_SIZE_WIDTH-3:0] mem_resp_idx;
|
|
|
|
// Current / Miss PC
|
// Current / Miss PC
|
reg [31:0] last_pc;
|
reg [31:0] last_pc_q;
|
reg [31:0] miss_pc;
|
reg [31:0] miss_pc_q;
|
|
|
// Flush state
|
// Flush state
|
reg flush_req;
|
reg flush_q;
|
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr;
|
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr_q;
|
reg flush_wr;
|
reg flush_wr_q;
|
|
|
// Other state
|
// Other state
|
reg initial_fetch;
|
reg read_while_busy_q;
|
reg read_while_busy;
|
|
|
|
// Current state
|
// Current state
|
parameter STATE_CHECK = 0;
|
parameter STATE_CHECK = 0;
|
parameter STATE_FETCH = 1;
|
parameter STATE_FETCH = 1;
|
parameter STATE_WAIT = 2;
|
parameter STATE_WAIT = 2;
|
parameter STATE_FLUSH = 3;
|
parameter STATE_FLUSH = 3;
|
reg [3:0] state;
|
reg [1:0] state_q;
|
|
|
// Tag address from input PC or flopped version of it
|
// Tag address from input PC or flopped version of it
|
assign tag_entry = (state != STATE_CHECK) ?
|
assign tag_address_w = (state_q != STATE_CHECK) ?
|
miss_pc[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] :
|
miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] :
|
pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
|
pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
|
|
|
// Cache read address
|
// Cache read address
|
assign cache_address_rd = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
|
assign address_rd_w = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
|
|
|
// Cache miss output if requested PC is not in the tag memory
|
// Cache miss output if requested PC is not in the tag memory
|
wire miss = (!tag_data_out[CACHE_TAG_VALID_BIT] ||
|
wire miss_w = ~tag_out_w[CACHE_TAG_VALID_BIT] |
|
(last_pc[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_data_out[14:0])) ? 1'b1: 1'b0;
|
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out_w[14:0]);
|
|
|
// Stall the CPU if cache state machine is not idle!
|
// Stall the CPU if cache state machine is not idle!
|
wire busy = (state == STATE_CHECK & ~read_while_busy) ? 1'b0 : 1'b1;
|
wire busy_w = (state_q != STATE_CHECK) | read_while_busy_q;
|
|
|
// Cache output valid
|
// Cache output valid
|
assign valid_o = !miss && !busy;
|
assign valid_o = busy_w ? 1'b0 : ~miss_w;
|
|
|
// Final word to fetch from memory
|
|
wire mem_fetch_final_word = (mem_fetch_word == {CACHE_LINE_WORDS_IDX_MAX{1'b1}});
|
|
|
|
// Flushing: Last line to flush
|
// Flushing: Last line to flush
|
wire flush_final_line = (flush_addr == {CACHE_LINE_ADDR_WIDTH{1'b0}});
|
wire flush_last_w = (flush_addr_q == {CACHE_LINE_ADDR_WIDTH{1'b0}});
|
|
|
// Is this a cache miss?
|
// Is this a cache miss?
|
wire cache_miss = (miss && // Tag lookup failed
|
wire cache_miss_w = miss_w & // Tag lookup failed
|
!initial_fetch && // NOT initial fetch after reset
|
!rd_i & // NOT new read request cycle
|
!rd_i && // NOT new read request cycle
|
!read_while_busy_q & // NOT pending read whilst busy
|
!read_while_busy && // NOT pending read whilst busy
|
!flush_q & // NOT flush request
|
!flush_req && // NOT flush request
|
!invalidate_i;
|
!invalidate_i);
|
|
|
wire mem_fetch_w = (state_q == STATE_CHECK) & cache_miss_w;
|
|
wire [31:0] mem_data_w;
|
|
wire [31:0] mem_resp_addr_w;
|
|
wire mem_valid_w;
|
|
wire mem_final_w;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Next State Logic
|
// Next State Logic
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [3:0] next_state_r;
|
reg [1:0] next_state_r;
|
always @ *
|
always @ *
|
begin
|
begin
|
next_state_r = state;
|
next_state_r = state_q;
|
|
|
case (state)
|
case (state_q)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache flush request pending?
|
// Cache flush request pending?
|
if (flush_req || invalidate_i)
|
if (flush_q || invalidate_i)
|
next_state_r = STATE_FLUSH;
|
next_state_r = STATE_FLUSH;
|
// Cache miss (& new read request not pending)
|
// Cache miss (& new read request not pending)
|
else if (cache_miss)
|
else if (cache_miss_w)
|
next_state_r = STATE_FETCH;
|
next_state_r = STATE_FETCH;
|
// Cache hit (or new read request)
|
// Cache hit (or new read request)
|
else
|
else
|
next_state_r = STATE_CHECK;
|
next_state_r = STATE_CHECK;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch row from memory
|
// FETCH - Fetch row from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH :
|
STATE_FETCH :
|
begin
|
begin
|
// Line fetch complete?
|
// Line fetch complete?
|
if (mem_resp_idx == {CACHE_LINE_SIZE_WIDTH-2{1'b1}} && wbm_ack_i)
|
if (mem_final_w)
|
next_state_r = STATE_WAIT;
|
next_state_r = STATE_WAIT;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FLUSH - Invalidate tag memory
|
// FLUSH - Invalidate tag memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FLUSH :
|
STATE_FLUSH :
|
begin
|
begin
|
if (flush_final_line)
|
if (flush_last_w)
|
next_state_r = STATE_FETCH;
|
next_state_r = STATE_CHECK;
|
else
|
else
|
next_state_r = STATE_FLUSH;
|
next_state_r = STATE_FLUSH;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WAIT - Wait cycle
|
// WAIT - Wait cycle
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WAIT :
|
STATE_WAIT :
|
next_state_r = STATE_CHECK;
|
next_state_r = STATE_CHECK;
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
|
|
// Update state
|
// Update state
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
state <= STATE_CHECK;
|
state_q <= STATE_FLUSH;
|
else
|
else
|
state <= next_state_r;
|
state_q <= next_state_r;
|
end
|
end
|
|
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Check for cache misses
|
// Flop request details
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
miss_pc <= BOOT_VECTOR + `VECTOR_RESET;
|
miss_pc_q <= BOOT_VECTOR + `VECTOR_RESET;
|
last_pc <= 32'h00000000;
|
last_pc_q <= 32'h00000000;
|
initial_fetch <= 1'b1;
|
|
read_while_busy <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
initial_fetch <= 1'b0;
|
last_pc_q <= pc_i;
|
last_pc <= pc_i;
|
|
|
|
// New request whilst cache busy?
|
case (state_q)
|
if (rd_i)
|
|
read_while_busy <= 1'b1;
|
|
|
|
case (state)
|
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache miss (& new read request not pending)
|
// Cache hit (or new read request), store fetch PC
|
if (cache_miss)
|
if (!cache_miss_w)
|
begin
|
miss_pc_q <= pc_i;
|
read_while_busy <= 1'b0;
|
|
|
|
`ifdef CONF_CORE_DEBUG
|
|
$display("Fetch: Cache miss at 0x%x (last=%x, current=%x)", miss_pc, last_pc, pc_i);
|
|
`endif
|
|
end
|
|
// Cache hit (or new read request)
|
|
else
|
|
begin
|
|
`ifdef CONF_CORE_DEBUG
|
|
$display("Fetch: Cache hit at PC=%x (current=%x)", last_pc, pc_i);
|
|
if (read_while_busy)
|
|
$display("Fetch: Read request whilst busy PC=%x (current=%x)", last_pc, pc_i);
|
|
`endif
|
|
// Store fetch PC
|
|
miss_pc <= pc_i;
|
|
read_while_busy <= 1'b0;
|
|
end
|
|
end
|
|
//-----------------------------------------
|
|
// FLUSH - Invalidate tag memory
|
|
//-----------------------------------------
|
|
STATE_FLUSH :
|
|
begin
|
|
// Last line, clear pending reads whilst busy
|
|
if (flush_final_line)
|
|
read_while_busy <= 1'b0;
|
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Cache Tag Write
|
// Detect new read request whilst busy
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
tag_data_in <= {CACHE_TAG_WIDTH{1'b0}};
|
read_while_busy_q <= 1'b0;
|
tag_wr <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tag_wr <= 1'b0;
|
case (state_q)
|
|
|
case (state)
|
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - Check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache miss (& new read request not pending)
|
read_while_busy_q <= 1'b0;
|
if (cache_miss)
|
|
begin
|
|
// Update tag memory with this line's details
|
|
tag_data_in <= {1'b1, miss_pc[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
|
|
tag_wr <= 1'b1;
|
|
end
|
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FLUSH - Invalidate tag memory
|
// OTHER - Fetching, flushing, waiting
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FLUSH :
|
default:
|
begin
|
|
if (flush_final_line)
|
|
begin
|
begin
|
// Update tag memory with this line's details
|
// New request whilst cache busy?
|
tag_data_in <= {1'b1, pc_i[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
|
if (rd_i)
|
tag_wr <= 1'b1;
|
read_while_busy_q <= 1'b1;
|
end
|
|
end
|
end
|
default:
|
|
;
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Flush Logic
|
// Cache Tag Write
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ *
|
begin
|
|
if (rst_i == 1'b1)
|
|
begin
|
|
flush_addr <= {CACHE_LINE_ADDR_WIDTH{1'b0}};
|
|
flush_wr <= 1'b0;
|
|
flush_req <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
begin
|
flush_wr <= 1'b0;
|
tag_in_r = {CACHE_TAG_WIDTH{1'b0}};
|
|
tag_wr_r = 1'b0;
|
|
|
// Latch invalidate request even if can't be actioned now...
|
case (state_q)
|
if (invalidate_i)
|
|
flush_req <= 1'b1;
|
|
|
|
case (state)
|
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache flush request pending?
|
// Cache miss (& new read request not pending)
|
if (flush_req || invalidate_i)
|
if (cache_miss_w)
|
begin
|
|
flush_req <= 1'b0;
|
|
flush_addr <= {CACHE_LINE_ADDR_WIDTH{1'b1}};
|
|
flush_wr <= 1'b1;
|
|
|
|
`ifdef CONF_CORE_DEBUG
|
|
$display("Fetch: Cache flush request");
|
|
`endif
|
|
end
|
|
end
|
|
//-----------------------------------------
|
|
// FLUSH - Invalidate tag memory
|
|
//-----------------------------------------
|
|
STATE_FLUSH :
|
|
begin
|
|
if (~flush_final_line)
|
|
begin
|
begin
|
flush_addr <= flush_addr - 1;
|
// Update tag memory with this line's details
|
flush_wr <= 1'b1;
|
tag_in_r = {1'b1, miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW]};
|
|
tag_wr_r = 1'b1;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// External Mem Access
|
// Flush Logic
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
reg flush_r;
|
|
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr_r;
|
|
reg flush_wr_r;
|
|
|
// Next fetch address
|
always @ *
|
wire [CACHE_LINE_SIZE_WIDTH-3:0] mem_next_word = mem_fetch_word + 1;
|
|
|
|
// Last word to fetch
|
|
wire mem_resp_idx_word = (mem_fetch_word == ({CACHE_LINE_WORDS_IDX_MAX{1'b1}}-1));
|
|
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
begin
|
|
wbm_addr_o <= 32'h00000000;
|
|
wbm_cti_o <= 3'b0;
|
|
wbm_stb_o <= 1'b0;
|
|
|
|
mem_fetch_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
end
|
|
else
|
|
begin
|
begin
|
if (~wbm_stall_i)
|
flush_wr_r = 1'b0;
|
wbm_stb_o <= 1'b0;
|
flush_addr_r = flush_addr_q;
|
|
flush_r = flush_q;
|
|
|
case (state)
|
case (state_q)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// CHECK - check cache for hit or miss
|
// CHECK - Check cache for hit or miss
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_CHECK :
|
STATE_CHECK :
|
begin
|
begin
|
// Cache miss (& new read request not pending)
|
// Cache flush request pending?
|
if (cache_miss)
|
if (flush_q || invalidate_i)
|
begin
|
begin
|
// Start fetch from memory
|
flush_r = 1'b0;
|
wbm_addr_o <= {miss_pc[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
flush_addr_r = {CACHE_LINE_ADDR_WIDTH{1'b1}};
|
|
flush_wr_r = 1'b1;
|
// Incrementing linear burst
|
|
wbm_cti_o <= 3'b010;
|
|
|
|
// Start of cycle
|
|
wbm_stb_o <= 1'b1;
|
|
|
|
mem_fetch_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch row from memory
|
// FLUSH - Invalidate tag memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH :
|
STATE_FLUSH :
|
begin
|
|
// Command accepted
|
|
if (~wbm_stall_i)
|
|
begin
|
|
// Fetch next word for line
|
|
if (!mem_fetch_final_word)
|
|
begin
|
begin
|
wbm_addr_o <= {wbm_addr_o[31:CACHE_LINE_SIZE_WIDTH], mem_next_word, 2'b00};
|
flush_addr_r = flush_addr_q - 1;
|
|
flush_wr_r = 1'b1;
|
// Final word to read?
|
|
if (mem_resp_idx_word)
|
|
wbm_cti_o <= 3'b111;
|
|
|
|
mem_fetch_word <= mem_next_word;
|
|
|
|
// Still fetching...
|
|
wbm_stb_o <= 1'b1;
|
|
end
|
|
end
|
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FLUSH - Invalidate tag memory
|
// OTHER - Fetching / wait cycles
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FLUSH :
|
default:
|
begin
|
|
// Fetch current PC line again
|
|
if (flush_final_line)
|
|
begin
|
begin
|
if (read_while_busy)
|
// Latch invalidate request even if can't be actioned now...
|
wbm_addr_o <= {miss_pc[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
if (invalidate_i)
|
else
|
flush_r = 1'b1;
|
wbm_addr_o <= {pc_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
|
|
|
// Incrementing linear burst
|
|
wbm_cti_o <= 3'b010;
|
|
|
|
// Start of cycle
|
|
wbm_stb_o <= 1'b1;
|
|
|
|
// Start of line
|
|
mem_fetch_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
end
|
|
end
|
end
|
default:
|
|
;
|
|
endcase
|
endcase
|
end
|
end
|
end
|
|
|
|
//-----------------------------------------------------------------
|
|
// CYC_O
|
|
//-----------------------------------------------------------------
|
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
wbm_cyc_o <= 1'b0;
|
|
else
|
|
begin
|
|
case (state)
|
|
|
|
//-----------------------------------------
|
|
// CHECK - check cache for hit or miss
|
|
//-----------------------------------------
|
|
STATE_CHECK :
|
|
begin
|
|
// Cache miss (& new read request not pending)
|
|
if (cache_miss)
|
|
wbm_cyc_o <= 1'b1;
|
|
end
|
|
//-----------------------------------------
|
|
// FLUSH - Invalidate tag memory
|
|
//-----------------------------------------
|
|
STATE_FLUSH :
|
|
begin
|
begin
|
// Fetch current PC line again
|
flush_addr_q <= {CACHE_LINE_ADDR_WIDTH{1'b1}};
|
if (flush_final_line)
|
flush_wr_q <= 1'b0;
|
wbm_cyc_o <= 1'b1;
|
flush_q <= 1'b0;
|
end
|
end
|
//-----------------------------------------
|
else
|
// FETCH - Fetch row from memory
|
|
//-----------------------------------------
|
|
STATE_FETCH :
|
|
begin
|
begin
|
// Last response?
|
flush_addr_q <= flush_addr_r;
|
if (wbm_ack_i && (mem_resp_idx == {CACHE_LINE_SIZE_WIDTH-2{1'b1}}))
|
flush_wr_q <= flush_wr_r;
|
wbm_cyc_o <= 1'b0;
|
flush_q <= flush_r;
|
end
|
|
default:
|
|
;
|
|
endcase
|
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Memory response counter
|
// External Mem Access
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
altor32_wb_fetch
|
begin
|
u_wb
|
if (rst_i == 1'b1)
|
(
|
mem_resp_idx <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
.clk_i(clk_i),
|
else
|
.rst_i(rst_i),
|
begin
|
|
case (state)
|
// Request
|
|
.fetch_i(mem_fetch_w),
|
|
.burst_i(1'b1),
|
|
.address_i(miss_pc_q),
|
|
|
//-----------------------------------------
|
|
// CHECK - check cache for hit or miss
|
|
//-----------------------------------------
|
|
STATE_CHECK :
|
|
begin
|
|
// Cache miss (& new read request not pending)
|
|
if (cache_miss)
|
|
mem_resp_idx <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
end
|
|
//-----------------------------------------
|
|
// FLUSH - Invalidate tag memory
|
|
//-----------------------------------------
|
|
STATE_FLUSH :
|
|
begin
|
|
// Fetch current PC line again
|
|
if (flush_final_line)
|
|
mem_resp_idx <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH - Fetch row from memory
|
|
//-----------------------------------------
|
|
STATE_FETCH :
|
|
begin
|
|
// Response
|
// Response
|
if (wbm_ack_i)
|
.resp_addr_o(mem_resp_addr_w),
|
mem_resp_idx <= mem_resp_idx + 1;
|
.data_o(mem_data_w),
|
end
|
.valid_o(mem_valid_w),
|
default:
|
.final_o(mem_final_w),
|
;
|
|
endcase
|
// Wishbone interface
|
end
|
.wbm_addr_o(wbm_addr_o),
|
end
|
.wbm_dat_i(wbm_dat_i),
|
|
.wbm_cti_o(wbm_cti_o),
|
|
.wbm_cyc_o(wbm_cyc_o),
|
|
.wbm_stb_o(wbm_stb_o),
|
|
.wbm_stall_i(wbm_stall_i),
|
|
.wbm_ack_i(wbm_ack_i)
|
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Tag memory
|
// Tag memory
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
altor32_ram_dp
|
altor32_ram_dp
|
#(
|
#(
|
.WIDTH(CACHE_TAG_WIDTH),
|
.WIDTH(CACHE_TAG_WIDTH),
|
.SIZE(CACHE_LINE_ADDR_WIDTH)
|
.SIZE(CACHE_LINE_ADDR_WIDTH)
|
)
|
)
|
u1_tag_mem
|
u1_tag_mem
|
(
|
(
|
// Tag read/write port
|
// Tag read/write port
|
.aclk_i(clk_i),
|
.aclk_i(clk_i),
|
.adat_o(tag_data_out),
|
.adat_o(tag_out_w),
|
.adat_i(tag_data_in),
|
.adat_i(tag_in_r),
|
.aadr_i(tag_entry),
|
.aadr_i(tag_address_w),
|
.awr_i(tag_wr),
|
.awr_i(tag_wr_r),
|
|
|
// Tag invalidate port
|
// Tag invalidate port
|
.bclk_i(clk_i),
|
.bclk_i(clk_i),
|
.badr_i(flush_addr),
|
.badr_i(flush_addr_q),
|
.bdat_o(/*open*/),
|
.bdat_o(/*open*/),
|
.bdat_i({CACHE_TAG_WIDTH{1'b0}}),
|
.bdat_i({CACHE_TAG_WIDTH{1'b0}}),
|
.bwr_i(flush_wr)
|
.bwr_i(flush_wr_q)
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Data memory
|
// Data memory
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
altor32_ram_dp
|
altor32_ram_dp
|
#(
|
#(
|
.WIDTH(32),
|
.WIDTH(32),
|
.SIZE(CACHE_DWIDTH)
|
.SIZE(CACHE_DWIDTH)
|
)
|
)
|
u2_data_mem
|
u2_data_mem
|
(
|
(
|
// Data read port
|
// Data read port
|
.aclk_i(clk_i),
|
.aclk_i(clk_i),
|
.aadr_i(cache_address_rd),
|
.aadr_i(address_rd_w),
|
.adat_o(instruction_o),
|
.adat_o(instruction_o),
|
.adat_i(32'h00),
|
.adat_i(32'h00),
|
.awr_i(1'b0),
|
.awr_i(1'b0),
|
|
|
// Data write port
|
// Data write port
|
.bclk_i(clk_i),
|
.bclk_i(clk_i),
|
.badr_i(cache_address_wr),
|
.badr_i(address_wr_w),
|
.bdat_o(/*open*/),
|
.bdat_o(/*open*/),
|
.bdat_i(wbm_dat_i),
|
.bdat_i(mem_data_w),
|
.bwr_i(cache_wr)
|
.bwr_i(cache_wr_w)
|
);
|
);
|
|
|
// Write to cache on wishbone response
|
// Write to cache on wishbone response
|
assign cache_address_wr = {miss_pc[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH], mem_resp_idx};
|
assign address_wr_w = {miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH], mem_resp_addr_w[CACHE_LINE_SIZE_WIDTH-1:2]};
|
|
|
assign cache_wr = (state == STATE_FETCH) & wbm_ack_i;
|
assign cache_wr_w = (state_q == STATE_FETCH) & mem_valid_w;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
