//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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// Module: Load / Store Unit
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// Module: Load / Store Unit
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module altor32_lsu
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module altor32_lsu
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(
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(
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// Current instruction
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// Current instruction
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input opcode_valid_i /*verilator public*/,
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input opcode_valid_i /*verilator public*/,
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input [7:0] opcode_i /*verilator public*/,
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input [7:0] opcode_i /*verilator public*/,
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|
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// Load / Store pending
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// Load / Store pending
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input load_pending_i /*verilator public*/,
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input load_pending_i /*verilator public*/,
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input store_pending_i /*verilator public*/,
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input store_pending_i /*verilator public*/,
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// Load dest register
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// Load dest register
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input [4:0] rd_load_i /*verilator public*/,
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input [4:0] rd_load_i /*verilator public*/,
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// Load insn in WB stage
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// Load insn in WB stage
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input load_wb_i /*verilator public*/,
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input load_wb_i /*verilator public*/,
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|
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// Memory status
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// Memory status
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input mem_access_i /*verilator public*/,
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input mem_access_i /*verilator public*/,
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input mem_ack_i /*verilator public*/,
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input mem_ack_i /*verilator public*/,
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// Load / store still pending
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// Load / store still pending
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output reg load_pending_o /*verilator public*/,
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output reg load_pending_o /*verilator public*/,
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output reg store_pending_o /*verilator public*/,
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output reg store_pending_o /*verilator public*/,
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// Insert load result into pipeline
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// Insert load result into pipeline
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output reg write_result_o /*verilator public*/,
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output reg write_result_o /*verilator public*/,
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// Stall pipeline due load / store / insert
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// Stall pipeline due load / store / insert
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output reg stall_o /*verilator public*/
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output reg stall_o /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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// Includes
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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`include "altor32_funcs.v"
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Outstanding memory access logic
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// Outstanding memory access logic
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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reg v_inst_load;
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reg v_inst_load;
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reg v_inst_store;
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reg v_inst_store;
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always @ *
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always @ *
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begin
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begin
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load_pending_o = load_pending_i;
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load_pending_o = load_pending_i;
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store_pending_o = store_pending_i;
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store_pending_o = store_pending_i;
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stall_o = 1'b0;
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stall_o = 1'b0;
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write_result_o = 1'b0;
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write_result_o = 1'b0;
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// Is this instruction a load or store?
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// Is this instruction a load or store?
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v_inst_load = is_load_operation(opcode_i);
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v_inst_load = is_load_operation(opcode_i);
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v_inst_store = is_store_operation(opcode_i);
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v_inst_store = is_store_operation(opcode_i);
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// Store operation just completed?
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// Store operation just completed?
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if (store_pending_o & mem_ack_i & ~mem_access_i)
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if (store_pending_o & mem_ack_i & ~mem_access_i)
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begin
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begin
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Store operation now completed");
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$display(" Store operation now completed");
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`endif
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`endif
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store_pending_o = 1'b0;
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store_pending_o = 1'b0;
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end
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end
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// Load just completed (and result ready in-time for writeback stage)?
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// Load just completed (and result ready in-time for writeback stage)?
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if (load_pending_o & mem_ack_i & ~mem_access_i & load_wb_i)
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if (load_pending_o & mem_ack_i & ~mem_access_i & load_wb_i)
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begin
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begin
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// Load complete
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// Load complete
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load_pending_o = 1'b0;
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load_pending_o = 1'b0;
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Load operation completed in writeback stage");
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$display(" Load operation completed in writeback stage");
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`endif
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`endif
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end
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end
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// Load just completed (later than writeback stage)?
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// Load just completed (later than writeback stage)?
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else if (load_pending_o & mem_ack_i & ~mem_access_i)
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else if (load_pending_o & mem_ack_i & ~mem_access_i)
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begin
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begin
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Load operation completed later than writeback stage");
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$display(" Load operation completed later than writeback stage");
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`endif
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`endif
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// Valid target register?
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// Valid target register?
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if (rd_load_i != 5'b00000)
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if (rd_load_i != 5'b00000)
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begin
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begin
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Load result now ready for R%d", rd_load_i);
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$display(" Load result now ready for R%d", rd_load_i);
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`endif
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`endif
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// Stall instruction and write load result to pipeline
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// Stall instruction and write load result to pipeline
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stall_o = opcode_valid_i;
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stall_o = opcode_valid_i;
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write_result_o = 1'b1;
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write_result_o = 1'b1;
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end
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end
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else
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else
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begin
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begin
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Load result ready but not needed");
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$display(" Load result ready but not needed");
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`endif
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`endif
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end
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end
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// Load complete
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// Load complete
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load_pending_o = 1'b0;
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load_pending_o = 1'b0;
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end
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end
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// If load or store in progress (and this instruction is valid)
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// If load or store in progress (and this instruction is valid)
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if ((load_pending_o | store_pending_o) & opcode_valid_i)
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if ((load_pending_o | store_pending_o) & opcode_valid_i)
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begin
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begin
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// Load or store whilst memory bus busy
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// Load or store whilst memory bus busy
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if (v_inst_load | v_inst_store)
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if (v_inst_load | v_inst_store)
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begin
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begin
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)", load_pending_o, store_pending_o);
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$display(" Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)", load_pending_o, store_pending_o);
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`endif
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`endif
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// Stall!
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// Stall!
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stall_o = 1'b1;
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stall_o = 1'b1;
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end
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end
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end
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end
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end
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end
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`include "altor32_funcs.v"
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endmodule
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endmodule
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