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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_lsu.v] - Diff between revs 36 and 37

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Rev 36 Rev 37
Line 8... Line 8...
//               Email: admin@ultra-embedded.com
//               Email: admin@ultra-embedded.com
//
//
//                       License: LGPL
//                       License: LGPL
//-----------------------------------------------------------------
//-----------------------------------------------------------------
//
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
//
// This source file may be used and distributed without         
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
// the original copyright notice and the associated disclaimer. 
Line 76... Line 76...
`include "altor32_funcs.v"
`include "altor32_funcs.v"
 
 
//-------------------------------------------------------------------
//-------------------------------------------------------------------
// Outstanding memory access logic
// Outstanding memory access logic
//-------------------------------------------------------------------
//-------------------------------------------------------------------
reg v_inst_load;
reg inst_load_r;
reg v_inst_store;
reg inst_store_r;
 
 
always @ *
always @ *
begin
begin
 
 
    load_pending_o   = load_pending_i;
    load_pending_o   = load_pending_i;
    store_pending_o  = store_pending_i;
    store_pending_o  = store_pending_i;
    stall_o          = 1'b0;
    stall_o          = 1'b0;
    write_result_o   = 1'b0;
    write_result_o   = 1'b0;
 
 
    // Is this instruction a load or store?
    // Is this instruction a load or store?
    v_inst_load     = is_load_operation(opcode_i);
    inst_load_r     = is_load_operation(opcode_i);
    v_inst_store    = is_store_operation(opcode_i);
    inst_store_r    = is_store_operation(opcode_i);
 
 
    // Store operation just completed?
    // Store operation just completed?
    if (store_pending_o & mem_ack_i & ~mem_access_i)
    if (store_pending_o & mem_ack_i & ~mem_access_i)
    begin
    begin
    `ifdef CONF_CORE_DEBUG
    `ifdef CONF_CORE_DEBUG
Line 142... Line 142...
 
 
    // If load or store in progress (and this instruction is valid)
    // If load or store in progress (and this instruction is valid)
    if ((load_pending_o | store_pending_o) & opcode_valid_i)
    if ((load_pending_o | store_pending_o) & opcode_valid_i)
    begin
    begin
        // Load or store whilst memory bus busy
        // Load or store whilst memory bus busy
        if (v_inst_load | v_inst_store)
        if (inst_load_r | inst_store_r)
        begin
        begin
    `ifdef CONF_CORE_DEBUG
    `ifdef CONF_CORE_DEBUG
            $display("   Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)",  load_pending_o, store_pending_o);
            $display("   Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)",  load_pending_o, store_pending_o);
    `endif
    `endif
            // Stall!
            // Stall!

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