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Line 52... |
input rd_i /*verilator public*/,
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input rd_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output valid_o /*verilator public*/,
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output valid_o /*verilator public*/,
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// Memory interface (slave)
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// Memory interface
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output reg [31:0] mem_addr_o /*verilator public*/,
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output reg [31:0] wbm_addr_o /*verilator public*/,
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input [31:0] mem_data_i /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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output reg mem_burst_o /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output reg mem_rd_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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input mem_accept_i/*verilator public*/,
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output reg wbm_stb_o /*verilator public*/,
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input mem_ack_i/*verilator public*/
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input wbm_stall_i/*verilator public*/,
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input wbm_ack_i/*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Current state
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// Current state
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parameter STATE_CHECK = 0;
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parameter STATE_CHECK = 0;
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parameter STATE_FETCH = 1;
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parameter STATE_FETCH = 1;
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reg [1:0] state;
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reg state;
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assign valid_o = mem_ack_i;
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reg ignore_resp;
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assign instruction_o = mem_data_i;
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assign valid_o = wbm_ack_i & ~ignore_resp & ~rd_i;
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assign instruction_o = wbm_dat_i;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Control logic
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// Control logic
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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mem_addr_o <= 32'h00000000;
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wbm_addr_o <= 32'h00000000;
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mem_rd_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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mem_burst_o <= 1'b0;
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wbm_cyc_o <= 1'b0;
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ignore_resp <= 1'b0;
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end
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end
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else
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else
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begin
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begin
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if (mem_accept_i)
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if (~wbm_stall_i)
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mem_rd_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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case (state)
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// CHECK - check cache for hit or miss
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// CHECK - check cache for hit or miss
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//-----------------------------------------
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//-----------------------------------------
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STATE_CHECK :
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STATE_CHECK :
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begin
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begin
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// Start fetch from memory
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// Start fetch from memory
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mem_addr_o <= pc_i;
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wbm_addr_o <= pc_i;
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mem_rd_o <= 1'b1;
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wbm_stb_o <= 1'b1;
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mem_burst_o <= 1'b0;
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wbm_cyc_o <= 1'b1;
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ignore_resp <= 1'b0;
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state <= STATE_FETCH;
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state <= STATE_FETCH;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// FETCH - Fetch row from memory
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// FETCH - Fetch row from memory
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//-----------------------------------------
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//-----------------------------------------
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STATE_FETCH :
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STATE_FETCH :
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begin
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begin
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// Read whilst waiting for previous response?
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if (rd_i)
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ignore_resp <= 1'b1;
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// Data ready from memory?
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// Data ready from memory?
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if (mem_ack_i)
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if (wbm_ack_i)
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begin
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wbm_cyc_o <= 1'b0;
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end
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end
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end
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default:
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default:
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;
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;
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endcase
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endcase
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end
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end
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end
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end
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assign wbm_cti_o = 3'b111;
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endmodule
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endmodule
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