//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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// Includes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - Cache substitute (used when ICache disabled)
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// Module - Cache substitute (used when ICache disabled)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module altor32_noicache
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module altor32_noicache
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(
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(
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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|
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// Processor interface
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// Processor interface
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input rd_i /*verilator public*/,
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input rd_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output valid_o /*verilator public*/,
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output valid_o /*verilator public*/,
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// Invalidate (not used)
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input invalidate_i /*verilator public*/,
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// Memory interface
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// Memory interface
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output reg [31:0] wbm_addr_o /*verilator public*/,
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output reg [31:0] wbm_addr_o /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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output reg wbm_stb_o /*verilator public*/,
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output reg wbm_stb_o /*verilator public*/,
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input wbm_stall_i/*verilator public*/,
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input wbm_stall_i/*verilator public*/,
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input wbm_ack_i/*verilator public*/
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input wbm_ack_i/*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Current state
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// Current state
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parameter STATE_CHECK = 0;
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parameter STATE_CHECK = 0;
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parameter STATE_FETCH = 1;
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parameter STATE_FETCH = 1;
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reg state;
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reg state;
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reg ignore_resp;
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reg ignore_resp;
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assign valid_o = wbm_ack_i & ~ignore_resp & ~rd_i;
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assign valid_o = wbm_ack_i & ~ignore_resp & ~rd_i;
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assign instruction_o = wbm_dat_i;
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assign instruction_o = wbm_dat_i;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Control logic
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// Control logic
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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wbm_addr_o <= 32'h00000000;
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wbm_addr_o <= 32'h00000000;
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wbm_stb_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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wbm_cyc_o <= 1'b0;
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wbm_cyc_o <= 1'b0;
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ignore_resp <= 1'b0;
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ignore_resp <= 1'b0;
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end
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end
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else
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else
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begin
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begin
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if (~wbm_stall_i)
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if (~wbm_stall_i)
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wbm_stb_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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case (state)
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// CHECK - check cache for hit or miss
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// CHECK - check cache for hit or miss
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//-----------------------------------------
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//-----------------------------------------
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STATE_CHECK :
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STATE_CHECK :
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begin
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begin
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// Start fetch from memory
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// Start fetch from memory
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wbm_addr_o <= pc_i;
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wbm_addr_o <= pc_i;
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wbm_stb_o <= 1'b1;
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wbm_stb_o <= 1'b1;
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wbm_cyc_o <= 1'b1;
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wbm_cyc_o <= 1'b1;
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ignore_resp <= 1'b0;
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ignore_resp <= 1'b0;
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state <= STATE_FETCH;
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state <= STATE_FETCH;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// FETCH - Fetch row from memory
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// FETCH - Fetch row from memory
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//-----------------------------------------
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//-----------------------------------------
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STATE_FETCH :
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STATE_FETCH :
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begin
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begin
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// Read whilst waiting for previous response?
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// Read whilst waiting for previous response?
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if (rd_i)
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if (rd_i)
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ignore_resp <= 1'b1;
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ignore_resp <= 1'b1;
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// Data ready from memory?
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// Data ready from memory?
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if (wbm_ack_i)
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if (wbm_ack_i)
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begin
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begin
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wbm_cyc_o <= 1'b0;
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wbm_cyc_o <= 1'b0;
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end
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end
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end
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end
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default:
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default:
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;
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;
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endcase
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endcase
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end
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end
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end
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end
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assign wbm_cti_o = 3'b111;
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assign wbm_cti_o = 3'b111;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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