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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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Line 56... |
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// Invalidate (not used)
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// Invalidate (not used)
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input invalidate_i /*verilator public*/,
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input invalidate_i /*verilator public*/,
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// Memory interface
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// Memory interface
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output reg [31:0] wbm_addr_o /*verilator public*/,
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output [31:0] wbm_addr_o /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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output wbm_cyc_o /*verilator public*/,
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output reg wbm_stb_o /*verilator public*/,
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output wbm_stb_o /*verilator public*/,
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input wbm_stall_i/*verilator public*/,
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input wbm_stall_i/*verilator public*/,
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input wbm_ack_i/*verilator public*/
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input wbm_ack_i/*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Current state
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// Current state
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parameter STATE_CHECK = 0;
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parameter STATE_CHECK = 0;
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parameter STATE_FETCH = 1;
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parameter STATE_FETCH = 1;
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reg state;
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reg state_q;
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reg ignore_resp;
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reg drop_resp_q;
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assign valid_o = wbm_ack_i & ~ignore_resp & ~rd_i;
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wire mem_fetch_w = (state_q == STATE_CHECK);
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assign instruction_o = wbm_dat_i;
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wire mem_valid_w;
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wire mem_final_w;
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//-----------------------------------------------------------------
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// Fetch unit
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//-----------------------------------------------------------------
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altor32_wb_fetch
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u_wb
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(
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.clk_i(clk_i),
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.rst_i(rst_i),
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.fetch_i(mem_fetch_w),
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.burst_i(1'b0),
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.address_i(pc_i),
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.resp_addr_o(/* not used */),
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.data_o(instruction_o),
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.valid_o(mem_valid_w),
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.final_o(mem_final_w),
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.wbm_addr_o(wbm_addr_o),
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.wbm_dat_i(wbm_dat_i),
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.wbm_cti_o(wbm_cti_o),
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.wbm_cyc_o(wbm_cyc_o),
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.wbm_stb_o(wbm_stb_o),
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.wbm_stall_i(wbm_stall_i),
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.wbm_ack_i(wbm_ack_i)
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Control logic
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// Control logic
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ (posedge rst_i or posedge clk_i )
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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wbm_addr_o <= 32'h00000000;
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drop_resp_q <= 1'b0;
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wbm_stb_o <= 1'b0;
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state_q <= STATE_CHECK;
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wbm_cyc_o <= 1'b0;
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ignore_resp <= 1'b0;
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state <= STATE_CHECK;
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end
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end
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else
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else
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begin
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begin
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case (state_q)
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if (~wbm_stall_i)
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wbm_stb_o <= 1'b0;
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case (state)
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//-----------------------------------------
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//-----------------------------------------
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// CHECK - check cache for hit or miss
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// CHECK - Accept read request
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//-----------------------------------------
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//-----------------------------------------
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STATE_CHECK :
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STATE_CHECK :
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begin
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begin
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// Start fetch from memory
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drop_resp_q <= 1'b0;
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wbm_addr_o <= pc_i;
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state_q <= STATE_FETCH;
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wbm_stb_o <= 1'b1;
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wbm_cyc_o <= 1'b1;
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ignore_resp <= 1'b0;
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state <= STATE_FETCH;
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end
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end
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//-----------------------------------------
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//-----------------------------------------
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// FETCH - Fetch row from memory
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// FETCH - Wait for read response
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//-----------------------------------------
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//-----------------------------------------
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STATE_FETCH :
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STATE_FETCH :
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begin
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begin
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// Read whilst waiting for previous response?
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// Read whilst waiting for previous response?
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if (rd_i)
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if (rd_i)
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ignore_resp <= 1'b1;
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drop_resp_q <= 1'b1;
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// Data ready from memory?
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// Data ready from memory?
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if (wbm_ack_i)
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if (mem_final_w)
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begin
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state_q <= STATE_CHECK;
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wbm_cyc_o <= 1'b0;
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state <= STATE_CHECK;
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end
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end
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end
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default:
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default:
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;
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;
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endcase
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endcase
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end
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end
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end
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end
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assign wbm_cti_o = 3'b111;
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assign valid_o = mem_valid_w & ~drop_resp_q & ~rd_i;
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assign instruction_o = wbm_dat_i;
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endmodule
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endmodule
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