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Line 37... |
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module: altor32_ram_dp - Dual port RAM (used in cache)
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// Module: altor32_ram_dp - Dual port RAM (used in cache)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module altor32_ram_dp
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module altor32_ram_dp
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#(
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parameter WIDTH = 8,
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parameter SIZE = 14
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)
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(
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(
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input aclk_i /*verilator public*/,
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input aclk_i /*verilator public*/,
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output [(WIDTH - 1):0] adat_o /*verilator public*/,
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output [(WIDTH - 1):0] adat_o /*verilator public*/,
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input [(WIDTH - 1):0] adat_i /*verilator public*/,
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input [(WIDTH - 1):0] adat_i /*verilator public*/,
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input [(SIZE - 1):0] aadr_i /*verilator public*/,
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input [(SIZE - 1):0] aadr_i /*verilator public*/,
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Line 56... |
input [(SIZE - 1):0] badr_i /*verilator public*/,
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input [(SIZE - 1):0] badr_i /*verilator public*/,
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input bwr_i /*verilator public*/
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input bwr_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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//-----------------------------------------------------------------
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parameter [31:0] WIDTH = 8;
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parameter [31:0] SIZE = 14;
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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/* verilator lint_off MULTIDRIVEN */
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/* verilator lint_off MULTIDRIVEN */
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reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
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reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
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/* verilator lint_on MULTIDRIVEN */
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/* verilator lint_on MULTIDRIVEN */
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