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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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/* verilator lint_off MULTIDRIVEN */
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/* verilator lint_off MULTIDRIVEN */
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reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
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reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
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/* verilator lint_on MULTIDRIVEN */
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/* verilator lint_on MULTIDRIVEN */
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reg [(SIZE - 1):0] rd_addr_a;
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reg [(SIZE - 1):0] rd_addr_a_q;
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reg [(SIZE - 1):0] rd_addr_b;
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reg [(SIZE - 1):0] rd_addr_b_q;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Processes
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// Processes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge aclk_i)
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always @ (posedge aclk_i)
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begin
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begin
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if (awr_i == 1'b1)
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if (awr_i == 1'b1)
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ram[aadr_i] <= adat_i;
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ram[aadr_i] <= adat_i;
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rd_addr_a <= aadr_i;
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rd_addr_a_q <= aadr_i;
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end
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end
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always @ (posedge bclk_i)
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always @ (posedge bclk_i)
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begin
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begin
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if (bwr_i == 1'b1)
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if (bwr_i == 1'b1)
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ram[badr_i] <= bdat_i;
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ram[badr_i] <= bdat_i;
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rd_addr_b <= badr_i;
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rd_addr_b_q <= badr_i;
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end
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end
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Combinatorial
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// Combinatorial
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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assign adat_o = ram[rd_addr_a];
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assign adat_o = ram[rd_addr_a_q];
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assign bdat_o = ram[rd_addr_b];
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assign bdat_o = ram[rd_addr_b_q];
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//-----------------------------------------------------------------
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// Init Memory
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//-----------------------------------------------------------------
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`ifdef ALTOR32_CLEAR_RAM
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integer i;
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initial
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begin
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for (i=0;i<((2<< (SIZE-1)) - 1);i=i+1)
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begin
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ram[i] = 0;
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end
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end
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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