| Line 37... |
Line 37... |
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Module: altor32_ram_sp - Single port RAM (used in cache)
|
// Module: altor32_ram_sp - Single port RAM (used in cache)
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
module altor32_ram_sp
|
module altor32_ram_sp
|
|
#(
|
|
parameter [31:0] WIDTH = 8,
|
|
parameter [31:0] SIZE = 14
|
|
)
|
(
|
(
|
input clk_i /*verilator public*/,
|
input clk_i /*verilator public*/,
|
output [(WIDTH - 1):0] dat_o /*verilator public*/,
|
output [(WIDTH - 1):0] dat_o /*verilator public*/,
|
input [(WIDTH - 1):0] dat_i /*verilator public*/,
|
input [(WIDTH - 1):0] dat_i /*verilator public*/,
|
input [(SIZE - 1):0] adr_i /*verilator public*/,
|
input [(SIZE - 1):0] adr_i /*verilator public*/,
|
input wr_i /*verilator public*/
|
input wr_i /*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
|
//-----------------------------------------------------------------
|
|
parameter [31:0] WIDTH = 8;
|
|
parameter [31:0] SIZE = 14;
|
|
|
|
//-----------------------------------------------------------------
|
|
// Registers
|
// Registers
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
|
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
|
reg [(SIZE - 1):0] rd_addr;
|
reg [(SIZE - 1):0] rd_addr;
|
|
|
