//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - Simple AltOR32 (wrapper for cutdown core)
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// Module - Simple AltOR32 (wrapper for cutdown core)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module cpu
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module cpu
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(
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(
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// General
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// General
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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|
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// Maskable interrupt
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// Maskable interrupt
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input intr_i /*verilator public*/,
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input intr_i /*verilator public*/,
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|
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// Unmaskable interrupt
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// Unmaskable interrupt
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input nmi_i /*verilator public*/,
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input nmi_i /*verilator public*/,
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|
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// Fault
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// Fault
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output fault_o /*verilator public*/,
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output fault_o /*verilator public*/,
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|
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// Breakpoint / Trap
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// Breakpoint / Trap
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output break_o /*verilator public*/,
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output break_o /*verilator public*/,
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|
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// Instruction memory (unused)
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// Instruction memory (unused)
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output [31:0] imem_addr_o /*verilator public*/,
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output [31:0] imem_addr_o /*verilator public*/,
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input [31:0] imem_dat_i /*verilator public*/,
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input [31:0] imem_dat_i /*verilator public*/,
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output [2:0] imem_cti_o /*verilator public*/,
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output [2:0] imem_cti_o /*verilator public*/,
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output imem_cyc_o /*verilator public*/,
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output imem_cyc_o /*verilator public*/,
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output imem_stb_o /*verilator public*/,
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output imem_stb_o /*verilator public*/,
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input imem_stall_i/*verilator public*/,
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input imem_stall_i/*verilator public*/,
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input imem_ack_i/*verilator public*/,
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input imem_ack_i/*verilator public*/,
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|
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// Memory interface
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// Memory interface
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output [31:0] dmem_addr_o /*verilator public*/,
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output [31:0] dmem_addr_o /*verilator public*/,
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input [31:0] dmem_dat_i /*verilator public*/,
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input [31:0] dmem_dat_i /*verilator public*/,
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output [31:0] dmem_dat_o /*verilator public*/,
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output [31:0] dmem_dat_o /*verilator public*/,
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output [2:0] dmem_cti_o /*verilator public*/,
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output [2:0] dmem_cti_o /*verilator public*/,
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output dmem_cyc_o /*verilator public*/,
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output dmem_cyc_o /*verilator public*/,
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output dmem_stb_o /*verilator public*/,
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output dmem_stb_o /*verilator public*/,
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output dmem_we_o /*verilator public*/,
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output dmem_we_o /*verilator public*/,
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output [3:0] dmem_sel_o /*verilator public*/,
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output [3:0] dmem_sel_o /*verilator public*/,
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input dmem_stall_i/*verilator public*/,
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input dmem_stall_i/*verilator public*/,
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input dmem_ack_i/*verilator public*/
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input dmem_ack_i/*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter BOOT_VECTOR = 32'h00000000;
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parameter BOOT_VECTOR = 32'h00000000;
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parameter ISR_VECTOR = 32'h00000000;
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parameter ISR_VECTOR = 32'h00000000;
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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parameter ENABLE_ICACHE = "DISABLED"; // Unused
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parameter ENABLE_ICACHE = "DISABLED"; // Unused
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parameter ENABLE_DCACHE = "DISABLED"; // Unused
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parameter ENABLE_DCACHE = "DISABLED"; // Unused
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parameter SUPPORT_32REGS = "ENABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Instantiation
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// Instantiation
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// CPU
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// CPU
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altor32_lite
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altor32_lite
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#(
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#(
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.BOOT_VECTOR(BOOT_VECTOR),
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.BOOT_VECTOR(BOOT_VECTOR),
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.ISR_VECTOR(ISR_VECTOR),
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.ISR_VECTOR(ISR_VECTOR),
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.REGISTER_FILE_TYPE(REGISTER_FILE_TYPE)
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.REGISTER_FILE_TYPE(REGISTER_FILE_TYPE)
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)
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)
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u_exec
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u_exec
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(
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(
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// General - clocking & reset
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// General - clocking & reset
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rst_i(rst_i),
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.fault_o(fault_o),
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.fault_o(fault_o),
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.break_o(break_o),
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.break_o(break_o),
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.nmi_i(nmi_i),
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.nmi_i(nmi_i),
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.intr_i(intr_i),
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.intr_i(intr_i),
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.enable_i(1'b1),
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.enable_i(1'b1),
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.mem_addr_o(dmem_addr_o),
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.mem_addr_o(dmem_addr_o),
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.mem_dat_o(dmem_dat_o),
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.mem_dat_o(dmem_dat_o),
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.mem_dat_i(dmem_dat_i),
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.mem_dat_i(dmem_dat_i),
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.mem_sel_o(dmem_sel_o),
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.mem_sel_o(dmem_sel_o),
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.mem_cti_o(dmem_cti_o),
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.mem_cti_o(dmem_cti_o),
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.mem_cyc_o(dmem_cyc_o),
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.mem_cyc_o(dmem_cyc_o),
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.mem_we_o(dmem_we_o),
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.mem_we_o(dmem_we_o),
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.mem_stb_o(dmem_stb_o),
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.mem_stb_o(dmem_stb_o),
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.mem_stall_i(dmem_stall_i),
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.mem_stall_i(dmem_stall_i),
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.mem_ack_i(dmem_ack_i)
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.mem_ack_i(dmem_ack_i)
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);
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);
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// Unused outputs
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// Unused outputs
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assign imem_addr_o = 32'b0;
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assign imem_addr_o = 32'b0;
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assign imem_cti_o = 3'b0;
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assign imem_cti_o = 3'b0;
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assign imem_cyc_o = 1'b0;
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assign imem_cyc_o = 1'b0;
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assign imem_stb_o = 1'b0;
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assign imem_stb_o = 1'b0;
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endmodule
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endmodule
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