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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`define ALU_ADDC 4'b0101
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`define ALU_ADDC 4'b0101
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`define ALU_SUB 4'b0110
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`define ALU_SUB 4'b0110
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`define ALU_AND 4'b0111
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`define ALU_AND 4'b0111
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`define ALU_OR 4'b1000
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`define ALU_OR 4'b1000
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`define ALU_XOR 4'b1001
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`define ALU_XOR 4'b1001
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`define ALU_COMPARE 4'b1010
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// ALU Instructions
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// ALU Instructions
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`define INST_OR32_ALU 8'h38
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`define INST_OR32_ALU 8'h38
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Set Flag Instructions
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// Set Flag Instructions
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`define INST_OR32_SFXX 8'h39
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`define INST_OR32_SFXX 8'h39
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`define INST_OR32_SFXXI 8'h2F
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`define INST_OR32_SFXXI 8'h2F
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`define INST_OR32_SFEQ 16'h0720
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`define INST_OR32_SFMASK 16'hFD3F
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`define INST_OR32_SFEQI 16'h05E0
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`define INST_OR32_SFEQ 16'h0520
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`define INST_OR32_SFGES 16'h072B
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`define INST_OR32_SFGES 16'h052B
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`define INST_OR32_SFGESI 16'h05EB
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`define INST_OR32_SFGEU 16'h0523
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`define INST_OR32_SFGEU 16'h0723
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`define INST_OR32_SFGTS 16'h052A
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`define INST_OR32_SFGEUI 16'h05E3
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`define INST_OR32_SFGTU 16'h0522
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`define INST_OR32_SFGTS 16'h072A
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`define INST_OR32_SFLES 16'h052D
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`define INST_OR32_SFGTSI 16'h05EA
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`define INST_OR32_SFLEU 16'h0525
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`define INST_OR32_SFGTU 16'h0722
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`define INST_OR32_SFLTS 16'h052C
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`define INST_OR32_SFGTUI 16'h05E2
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`define INST_OR32_SFLTU 16'h0524
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`define INST_OR32_SFLES 16'h072D
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`define INST_OR32_SFNE 16'h0521
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`define INST_OR32_SFLESI 16'h05ED
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`define INST_OR32_SFLEU 16'h0725
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`define INST_OR32_SFLEUI 16'h05E5
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`define INST_OR32_SFLTS 16'h072C
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`define INST_OR32_SFLTSI 16'h05EC
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`define INST_OR32_SFLTU 16'h0724
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`define INST_OR32_SFLTUI 16'h05E4
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`define INST_OR32_SFNE 16'h0721
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`define INST_OR32_SFNEI 16'h05E1
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Misc Instructions
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// Misc Instructions
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`define INST_OR32_MISC 8'h08
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`define INST_OR32_MISC 8'h08
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