OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [fpga/] [bin/] [Makefile] - Diff between revs 61 and 63

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 61 Rev 63
Line 88... Line 88...
else
else
    AMBER_CORE = AMBER_A23_CORE
    AMBER_CORE = AMBER_A23_CORE
endif
endif
 
 
 
 
## FPGA type
 
ifdef VIRTEX6
 
    # Virtex-6 device
 
    XILINX_FPGA     = xc6vlx75tff784-3
 
    XST_DEFINES     = XILINX_FPGA XILINX_VIRTEX6_FPGA  $(AMBER_CORE) AMBER_CLK_DIVIDER=15 $(BOOT_LOADER_DEF)
 
    # Xilinx placement and timing constraints
 
    XST_CONST_FILE  = xv6_constraints.ucf
 
    # List of verilog source files for Xilinx Virtex-6 device
 
    XST_PROJ_FILE   = xv6_source_files.prj
 
else
 
    # The spartan6 device used on SP605 Development board
    # The spartan6 device used on SP605 Development board
    XILINX_FPGA     = xc6slx45tfgg484-3
    XILINX_FPGA     = xc6slx45tfgg484-3
    XST_DEFINES     = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 $(BOOT_LOADER_DEF)
    XST_DEFINES     = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 $(BOOT_LOADER_DEF)
    # Xilinx placement and timing constraints
    # Xilinx placement and timing constraints
    XST_CONST_FILE  = xs6_constraints.ucf
    XST_CONST_FILE  = xs6_constraints.ucf
    # List of verilog source files for Xilinx Spartan-6 device
    # List of verilog source files for Xilinx Spartan-6 device
    XST_PROJ_FILE   = xs6_source_files.prj
    XST_PROJ_FILE   = xs6_source_files.prj
endif
 
 
 
 
 
# ----------------------------------------------------
# ----------------------------------------------------
# Focus on speed or area
# Focus on speed or area
# ----------------------------------------------------
# ----------------------------------------------------
Line 187... Line 178...
        @echo "              clean      Delete all temporary files"
        @echo "              clean      Delete all temporary files"
        @echo "              bitgen     Create a bitfile. Don't run trce"
        @echo "              bitgen     Create a bitfile. Don't run trce"
        @echo "              trce       Running timing analysis. Don't run buitgen"
        @echo "              trce       Running timing analysis. Don't run buitgen"
        @echo "              help       Print this message"
        @echo "              help       Print this message"
        @echo ""
        @echo ""
        @echo "Optional switches: VIRTEX6=1 A25=1 WORK="
        @echo "Optional switches: A25=1 WORK="
        @echo "e.g. > make VIRTEX6=1 WORK=work1 map"
        @echo "e.g. > make A25=1 WORK=work1 map"
 
 
clean :
clean :
        rm -Rf   $(WORK_FOLDER)/*
        rm -Rf   $(WORK_FOLDER)/*
 
 
cleanmap :
cleanmap :

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.